Sensitivity Analysis of Continuous-Time $\Delta \Sigma$ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers

Saad, Ramy A.; Aristizabal-Ramirez, D. L.; Hoyos, Sebastián

doi:10.1109/tcsi.2012.2185310

Cited by 13 publications

(2 citation statements)

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“…Within the dynamic linear range, the¯rst and last points are used to evaluate the slope between the delay on y-axis and V IN on x-axis. 1 The slope represents the circuit sensitivity which equals to 0.1 ps/mV and 0.09 ps/mV for the proposed design and the single-ended design, respectively. The proposed design shows a higher sensitivity than the single-ended design as the sensitivity is a function of the delay which is enhanced due to the di®erential mechanism.…”

Section: Voltage Sensitivitymentioning

confidence: 99%

“…Nowadays, the°ow of scaling CMOS technology invades all industrial and scienti¯c communities. This drift overcomes the main problems that face conventional Analog-to-Digital Converters (ADCs) [1][2][3][4] to satisfy the Software-De¯ned Radio (SDR) applications requirements. In fact, due to the capacity of demands, a single chip is intended to have several chains of transmitting and receiving blocks needed for di®erent wireless standards that require from the ADC: a high sampling frequency and a wide dynamic range.…”

Section: Introductionmentioning

confidence: 99%

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A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit

El-Bayoumi

Mostafa

Soliman

2017

J CIRCUIT SYST COMP

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Time-based Analog-to-Digital Converter (TADC), plays a major role in designing Software-Defined Radio (SDR) receivers, at scaled CMOS technologies, as it manifests lower area and power than conventional ADCs. TADC consists of 2 major blocks. The input voltage is converted into a pulse delay using a Voltage-to-Time Converter (VTC). In additions, the pulse delay is converted into a digital word using a Time-to-Digital Converter (TDC). In this paper, a novel fully-differential VTC based on a new methodology is presented which reports a highly-linear design. A metal-insulator-metal (MIM) capacitor as well as a dynamic calibration technique based on a set of large-sized capacitor-based voltage dividers circuits are utilized to automatically compensate the Process-Voltage-Temperature (PVT) variations. Moreover, the layout design is introduced. The proposed design operates on a 1[Formula: see text]GS/s sampling frequency with a supply voltage of 1.2[Formula: see text]V. After calibration, simulation results, using TSMC 65[Formula: see text]nm CMOS technology, report a 1.42[Formula: see text]V wider dynamic range due to the differential mechanism with a 3% linearity error. This design achieves a resolution up to 14 bits, a 0.07 fJ/conversion FOM, a 229[Formula: see text][Formula: see text]m2 area and a 0.25[Formula: see text]mW power. The simulation results are compared to the single-ended VTC results and the state-of-the-art analog-part ADCs results to show the strength of the proposed design.

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Section: Voltage Sensitivitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%