Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach

Abstract

Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5 ps rms clock jitter. In comparison, existing architectures based on time-interleaving require 0 5 ps rms clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications. Index Terms-Baseband receivers, channel bank filters, jitter. I. INTRODUCTION I MAGINE the potential offered if electronic devices, such as computers, cell phones, digital cameras, MP3 players, flat panels, and external hard disks wirelessly connect to each other at speeds similar to the processing capabilities of modern computers. Although it is clear that advances in the semiconductor industry provide some of the tools for these ideas to become reality [millimeter-wave radio (mmWR) [1], [2], software-defined radio [3], [4], cognitive radio (CR) [5], [6], [54] and multistandard radio [4], [7]], there remain challenging issues that prevent wireless multichannel systems from coming to fruition. For instance, in applications such as power-spectral-density estimation for CRs [6], [8] and future mmWR standards, several gigahertz of bandwidth with high dynamic-range Manuscript

A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End

“…On the other hand, the performance of Nyquist rate ADCs such as time-interleaved ADCs is limited by the sampling clock jitter that degrades the S/H performance as follows [26], [40]: (4) A comparison of this SNR with that of (3) shows that the conventional solutions using a S/H running at the Nyquist rate demands lower clock jitter than the proposed system.…”

“…The ADC speed is pushed towards the limit of the technology and both power consumption and jitter effects increase significantly. One way to lower the power consumption is to design a front-end that utilizes several ADCs to provide a combined sampling rate, such as time-interleaving structures [7]- [11] and multi-channel filter-bank approaches [12], [13], [40]. In these cases, the overall system is still operating at the Nyquist rate, so the total power reduction is limited.…”

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