As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Compared to a simple extension of an existing switch block, our new architecture leads to an 8.7% improvement in density with little effect on speed. Finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 1.1%.
Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current toolchains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable powergating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.
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Configuration of an application-specific instruction-set processor (ASIP) through an exhaustive search of the design space is computationally prohibitive. We propose a novel algorithm that models the design space using local regressions. With only a small subset of the design space sampled, our model uses statistical inference to estimate all remaining points. We used our approach to tune a two-level cache with 19,278 legal configurations. Only 1% of the design space was simulated resulting in a 100x speedup over a brute-force approach. In doing so, we were able to identify near optimal configurations for most benchmarks and reduce the overall power of the processor by 13.9% on average, with one benchmark as high as 53%.
The dynamic partial reconfiguration of FPGAs is a method which modifies parts of FPGA configuration memory at run-time. The hardware resources and time overhead needed to perform a partial reconfiguration (PR) can significantly impact overall system cost and performance and must be considered early in the design cycle. Unfortunately, predicting reconfiguration overhead is difficult especially in the presence of non-deterministic factors such as the sharing of resources with traffic not related to the PR process. Thus, current design practices include the measurement of overhead but only after the system has been built thus limiting the number of candidates that can be evaluated. We propose a flexible approach for modeling the PR datapath based on Queueing Theory such that we can estimate performance trends and bottlenecks of the PR process while considering the impact of shared resources. Performance trends are provided for an example system to demonstrate the effectiveness of the approach.
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