High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Abstract

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current toolchains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable powergating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

“…Thus, there exists a general agreement among the designers regarding the significance of system-level power optimization techniques [Ahmed et al 2014;Bezati et al 2014]. Commercial efforts in producing pre-RTL power optimization tools have resulted in tools such as Vista Architect from Mentor Graphics and Chip vision's PowerOpt TM ,.…”