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Abstract-ModernSoCs are getting increasingly heterogeneous with a combination of multi-core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High-level Synthesis (HLS) simplifies FPGA programming by allowing designers to program FPGAs in several high-level languages e.g. C/C++, OpenCL and SystemC.This work focuses on using an HLS based methodology to implement a widely used classification algorithm i.e. k-nearest neighbor on an FPGA based platform directly from its OpenCL code. Multiple fairly different implementations of the algorithm are considered and their performance on FPGA and GPU is compared. It is concluded that the FPGA generally proves to be more power efficient as compared to the GPU. Furthermore, using an FPGA-specific OpenCL coding style and providing appropriate HLS directives can yield an FPGA implementation comparable to a GPU also in terms of execution time.

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High-level synthesis (HLS) offers several advantages, such as faster simulation run-time and better design re-use, thanks to the higher level of abstraction. This work uses HLS to implement the Semi-Global Matching (SGM) algorithm, which is frequently used in stereo vision systems, e.g. for automotive applications. The hardware implementation is based on a Xilinx ® Virtex 7 FPGA. The initial algorithmic "golden" model used very large arrays, which had to be mapped to an external DRAM and brought into the on-chip RAM of the FPGA on demand. This required both adding the memory transfer loops and inserting calls to the AXI transactors that access the DRAM through the on-chip DDR slave. Moreover, the initial single-threaded algorithm had to be parallelized, by converting the top-level sweeps of the image in eight directions into as many threads. The access to the DRAM was then managed with a centralized controller. This modified SystemC design proved to be suitable to achieve the target real-time performance. The design space was thus explored by making several fairly different micro-architectural choices. In the end, it was possible to obtain an implementation which is comparable to a very efficient (and hence very inflexible) manual RTL design that had been previously developed, including a very sophisticated fine-grained management of data and computation.

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This paper presents line-interactive transformerless Uninterruptible Power Supply (UPS) with a fuel cell as the prime energy source. The proposed UPS consists of three major parts (i.e., an output inverter, a unidirectional DC-DC converter, and a battery charger/discharger). Non-isolated topologies of both the unidirectional converter and battery charger/discharger ensure transformerless operation of the UPS system. A new topology of high gain converter is employed for boosting the low voltage of the fuel cell to a higher DC link voltage, with minimum semiconductor count, and high efficiency. A high-gain battery charger/discharger realizes the bidirectional operation between the DC link and the battery bank. Besides, it regulates the DC link voltage during the cold start of fuel cells and keeps the battery bank voltage to only 24 V. A new inverter control scheme is introduced that regulates the output voltage and minimizes the total harmonic distortion for non-linear loading condition. The proposed control scheme integrates proportional-resonant control with slide mode control, which improves the controller's performance in transient conditions. The proposed UPS system is validated by developing a 1-kVA experimental prototype.

The abstraction level for digital designs is rising from Register Transfer Level (RTL) to algorithmic untimed or transaction-based, followed by an automated high level synthesis (HLS) flow. However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system level. Nowadays, low power design techniques for digital blocks are applied at RTL and there exists no commercial tool or methodology that can automatically derive the power intent from the system level description. The process requires considerable amount of human intervention and various lower-level details that are needed to implement low power schemes at RTL. This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology. The methodology aims at minimizing the design effort for low power design by deriving low-level power intent automatically for model-based designs, while using high level synthesis to achieve a broad set of target system implementations. All the information that is needed to implement low power techniques is automatically derived from the systemlevel design using a set of pragmas and a directives file. To illustrate the methodology, three model designs, ranging from simple designs to medium complexity hardware accelerators, are considered. Finally, the power saving results for the design scenarios validate the effectiveness of our LP-HLS methodology. • Hardware~Best practices for EDA • Hardware~Software tools for EDA • Hardware~Hardware description languages and compilation • Hardware~Modeling and parameter extractionAdditional Key Words and Phrases: Hardware accelerators, HLS, RTL, design space exploration, common power format, low power designs, design automation.

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