High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis

Ma, Liang; Muslim, Fahad Bin; Lavagno, Luciano

doi:10.1109/ems.2016.036

Cited by 6 publications

(6 citation statements)

References 10 publications

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“…To quantify this, we used accelerators of three different types of size: sparse (AES), medium (Normal Est. [27]) and dense (Black Scholes [22]). The utilization for each is 33%, 63% and 81%, respectively.…”

Section: Compilationmentioning

confidence: 99%

“…16. Place and route result of Black Scholes accelerator [22] for Xilinx PR flow and FOS. Note, FOS uses BitMan [26] to generate a relocatable bitstream which is copied to the other PR regions.…”

Section: Compilationmentioning

confidence: 99%

“…Total place and route (P&R) times, and bitstream generation latency for AES, Normal Est. [27], and Black Scholes accelerator [22] when compiling for all three partial regions on Ultra-96 shell. The evaluation is conducted using Vivado 2018.2.1 on an Intel core i7-4930K CPU running at 3.4 GHz with 64 GB of RAM.…”

Section: Compilationmentioning

confidence: 99%

“…To understand the effects of exposing more parallelism than available on the FPGA platform, we conducted the experiments on Ultra-96 using compute-bound (Mandelbrot and Black Scholes [22]) and memory-bound (Sobel [46]) applications which are more sensitive to reconfiguration overhead due to their smaller execution latencies than Spector benchmarks [27]. Figure 20 shows the results in which the number of requests dictates the amount of parallelism exposed to the runtime system.…”

Section: Application Case Studymentioning

confidence: 99%

“…20. Execution latencies of Mandelbrot, Black Scholes (European option) [22], and Sobel [46] when executing concurrently with varying the number of hardware requests on the Ultra-96 platform. Mandelbrot Black-Scholes Sobel Fig.…”

Section: Multi-tenant Dynamic Offloadmentioning

confidence: 99%

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ACM Trans. Reconfigurable Technol. Syst.

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With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods that can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application developers. However, current FPGA systems fail to achieve modularity and support for multi-tenancy due to dependencies between system components and the lack of standardised abstraction layers. To solve this, we introduce a modular FPGA operating system – FOS, which adopts a modular FPGA development flow to allow each system component to be changed and be agnostic to the heterogeneity of EDA tool versions, hardware and software layers. Further, to dynamically maximise the utilisation transparently from the users, FOS employs resource-elastic scheduling to arbitrate the FPGA resources in both time and spatial domain for any type of accelerators. Our evaluation on different FPGA boards shows that FOS can provide performance improvements in both single-tenant and multi-tenant environments while substantially reducing the development time and, at the same time, improving flexibility.

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Section: Compilationmentioning

confidence: 99%

Section: Compilationmentioning

confidence: 99%