FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs

Zahir, Ali; Khattak, Shadan; Ullah, Anees; Reviriego, Pedro; Muslim, Fahad Bin; Ahmad, Waleed

doi:10.1109/tvlsi.2020.3026840

Cited by 7 publications

(11 citation statements)

References 23 publications

(26 reference statements)

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“…It increases area performance by at least 67 percent and energy efficiency by at least 2.5 times. Frac-TCAM [27] utilizes RAM32M to construct the 8 × 5 TCAM compared to 4 × 6 TCAM used in DURE, thus almost doubling the utilization density. Moreover, LUTRAM outputs can be pipelined via in-slice registers.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

2022

Informacije MIDEM

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Ternary Content Addressable Memories [TCAM] based on Field Programmable Gate Arrays [FPGA] are widely used in artificial intelligence [AI] and networking applications. TCAM macros are unavailable within the FPGA; therefore, they must be emulated using SRAM-based memories, which require FPGA resources. Compared to state-of-the-art designs, the proposed FPGAbased TCAM implementation will save significant resources. This methodology makes use of the Lookup Table RAMS (LUTRAMs), slice carry-chains, and flip-flops (FF) allowing simultaneous mapping of rules and deeper pipelining respectively. The TCAM implementation results in lower power consumption, fewer delays and lower resource utilization. It outperforms conventional FPGA-based TCAMs in terms of energy efficiency (EE) and performance per area (PA) by at least 3.34 and 8.4 times respectively, and 56% better than existing FPGA designs. The proposed method outperforms all previous approaches due to its low dynamic power consumption when considering the huge size of TCAM emulation on SRAM-based FPGAs.

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Section: Related Workmentioning

confidence: 99%

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

2022

Informacije MIDEM

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“…The P4‐NetFPGA implementation of each forwarding scheme was analyzed for resource utilization using the Xilinx Vivado design suite 32 . The major resource types measured were: FFs, lookup tables (LUT), lookup table used for storage (LUTRAM) and block RAM (BRAM) are presented 33 . These are the basic reconfigurable units that are used to implement the required logic on an FPGA.…”

Section: Netfpga‐based Performance Studiesmentioning

confidence: 99%

“…32 The major resource types measured were: FFs, lookup tables (LUT), lookup table used for storage (LUTRAM) and block RAM (BRAM) are presented. 33 These are the basic reconfigurable units that are used to implement the required logic on an FPGA. Here, FFs are used to realize registers.…”

Section: Experiments Detailsmentioning

confidence: 99%

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

Sankaran¹,

Sivalingam

2021

Trans Emerging Tel Tech

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This paper studies how high-performance computer servers, equipped with Field-Programmable Gate Arrays (FPGAs), can perform high-speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits-per-second.The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address-based Longest Prefix Matching and Multi-Protocol Label Switching tag-based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on-demand increase of packet routing capacity in data center networks and support for Network Function Virtualization-based systems.

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“…They can be classified as the first kind that are characterized by a large memory unit (generally 36K-bit for BRAM and 288Kbit for URAM). Besides, D-TCAM [19] and its improved variant FracTCAM [20] utilize dual-port distributed LUT RAM that has a medium unit size of 64 × 4 bits. In addition, there are TCAMs that make use of a shift register look-up table (SRL) [16], LUT [21], and flip-flops [22][23][24].…”

Section: Introductionmentioning

confidence: 99%

“…Generally speaking, BRAM-based TCAM has longer update latency and lower resource efficiency as its SRAM/TCAM bit ratio is at least 2 9 /9 [20]. FF-based TCAM is only suitable for shallow TCAMs where update latency is critical [22].…”

Section: Introductionmentioning

confidence: 99%

MAToC: A Novel Match-Action Table Architecture on Corundum for 8 × 25G Networking

2022

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Packet processing offloads are increasingly needed by high-speed networks. This paper proposes a high throughput, low latency, scalable and reconfigurable Match-Action Table (MAT) architecture based on the open source FPGA-based NIC Corundum. The flexibility and capability of this scheme is demonstrated by an example implementation of IP layer forwarding offload. It makes the NIC work as a router that can forward packets for different subnet and virtual local area networks (VLAN). Experiments are performed on a Zynq MPSoC device with two QSFPs and the results show that it can work at line rate of 8 × 25 Gbps (200 Gbps), within a maximum latency of 76 nanoseconds. In addition, a high-performance MAT pipeline with full-featured, resource-efficient TCAM and a compact frame merging deparser are presented.

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FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs

Cited by 7 publications

References 23 publications

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

MAToC: A Novel Match-Action Table Architecture on Corundum for 8 × 25G Networking

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