Detailed routing architectures for embedded programmable logic IP cores

Hallschmid, Peter; Wilton, Steven J. E.

doi:10.1145/360276.360300

Cited by 16 publications

(10 citation statements)

References 9 publications

(11 reference statements)

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“…The use of this basic architecture to create FPGAs with wires that span multiple logic blocks is described in [10]. This design is extended in [6] to generate rectangular switch blocks, were the number of vertical and horizonal tracks is not necessarily equal. Other empirical studies include [8,11].…”

Section: Related Workmentioning

confidence: 99%

“…In papers such as [11,12,10,6], as well as the VPR tool, layout area is modeled as a linear relationship with the number of switches, which fails to consider the connections between those switches. Our study focusses on the issue of interconnection and placement of configuration and switch resources.…”

Section: Related Workmentioning

confidence: 99%

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Our final motivation for this effort is that future chip design methodologies may incorporate an FPGA fabric as a core on an ASIC, as described in [6]. Ideally, such FPGA cores could vary the mix of interconnect and cell functionality based on the application domain, the length of the wire segments, and other parameters.…”

Section: Introductionmentioning

confidence: 99%

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FPGA switch block layout and evaluation

Schmit

Chandra

2002

Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays - FPGA '02

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This paper presents abstract layout techniques for a variety of FPGA switch block architectures. We evaluate the relative density of subset, universal, and Wilton switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks, and good results for large switch blocks. For switch blocks with general connectivity, we develop a representation and a layout evaluation technique. We use these techniques to compare a variety of small switch blocks. We find that the traditional Xilinx-style, subset switch block is superior to the other proposed architectures. Finally, we have hand-designed some small switch blocks to confirm our results.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FPGA switch block layout and evaluation

Schmit

Chandra

2002

Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays - FPGA '02

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“…It is based on the VPR [3] architecture exploration system, which is an architectureretargettable packing, placement and routing system. FPGA architects use VPR to explore different architectural alternatives by changing the architecture across a spectrum of choices, and running a number of benchmark circuits through each architecture [2][3] [4][6] [7] [17]. The output of VPR provides circuit speed and area requirements for each circuit implemented on each architecture, allowing the architect to determine the value of different choices.…”

Section: Introductionmentioning

confidence: 99%

Automatic transistor and physical design of FPGA tiles from an architectural specification

Padalia

Fung

Bourgeault

et al. 2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this paper we present a new system (called GILES, for Good Instant Layout of Erasable Semiconductors) that automatically generates a transistor-level schematic from a high-level architectural specification of an FPGA. It also generates a cell-level netlist that is placed and routed automatically. The architectural specification is the one used as input to the VPR [3] architectural exploration tool. The output is the mask-level layout of a single tile that can be replicated to form an FPGA array. We describe a new placement tool that simultaneously places and compacts the layout to minimize white space and wiring demand, and a specialpurpose router built for this task.GILES can place and route a tile consisting of four 4-input LUT logic cells and all of its programmable wires in a 0.18µm CMOS process using 8 layers of metal and 25983µm 2 of area. When we generate the layout of an architecture similar to the Xilinx Virtex-E FPGA (built in a 0.18µm process) GILES requires only 47% more area than the original. The layout area of an architecture similar to the Altera Apex 20K400E (also built in a 0.18µm process) constructed by GILES requires 97% more area than the original.

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“…Second, we investigate how this efficiency changes as the dimensions of the core change. In [8], it was shown that the efficiency of a rectangular core is less than that of a square core, and that the efficiency drops as the core gets more and more rectangular. In this section, we investigate whether this is true for our non-rectangular cores.…”

Section: Architecture Studymentioning

confidence: 99%