We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on ntype Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. 2These features render the device a photodetector with responsivity (3 / for white LED light at 3 2 ⁄ intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution.This work represents a significant advance in the realization of graphene/Si Schottky devices for optoelectronic applications.

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The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

We report the observation of field emission (FE) from InP nanocrystals (NCs) epitaxially grown on an array of p-Si nanotips. We prove that FE can be enhanced by covering the InP NCs with graphene. The measurements are performed inside a scanning electron microscope chamber with a nano-controlled W-thread used as an anode. We analyze the FE by Fowler-Nordheim theory and find that the field enhancement factor increases monotonically with the spacing between the anode and the cathode. We also show that InP/p-Si junction has a rectifying behavior, while graphene on InP creates an ohmic contact. Understanding the fundamentals of such nanojunctions is key for applications in nanoelectronics.

Dislocation networks are one of the most principle sources deteriorating the performances of devices based on lattice-mismatched heteroepitaxial systems. We demonstrate here a technique enabling fully coherent Ge islands selectively grown on nano-tip patterned Si (001) substrates. The Si-tip patterned substrate, fabricated by complementary metal-oxidesemiconductor (CMOS) compatible nanotechnology, features ~50 nm wide Si areas emerging from a SiO 2 matrix and arranged in an ordered lattice. Molecular beam epitaxy (MBE) growths result in Ge nano-islands with high selectivity and having homogeneous shape and size. The ~850°C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 at.% Ge). Nano-tip patterned wafers result in geometric, kinetic diffusion barrier intermixing hindrance confining the major intermixing to the pedestal region of Ge islands where kinetic diffusion barriers are however high. Theoretical calculations suggest that the thin SiGe layer at the interface plays nevertheless a significant role in realizing our fully coherent Ge nano-islands free from extended defects especially dislocations. Single layer graphene (SLG)/Ge/Si-tip Schottky junctions were fabricated and thanks to the absence of extended defect in Ge islands, they demonstrate high performance photodetection characteristics with responsivity and I on /I off ratio of ~45 mA/W and ~10 3 , respectively.

The threading dislocation density (TDD) in plastically relaxed Ge/Si(001) heteroepitaxial films is commonly observed to progressively decrease with their thickness, owing to mutual annihilation. However, there exists a saturation limit, known as the geometrical limit, beyond which a further decrease of the TDD in the Ge film is hindered. Here, we show that such limit can be overcome in SiGe/Ge/Si heterostructures thanks to the beneficial role of the second interface.Indeed, we show that Si0.06Ge0.94/Ge/Si(001) films display a TDD remarkably lower than the saturation limit of Ge/Si(001). Such result is interpreted with the help of Dislocation Dynamics simulations. The reduction of TDD is attributed to the enhanced mobility acquired by pre-existing threading dislocations after bending at the new interface to release the strain in the upper layer.Importantly, we demonstrate that the low TDD achieved in Si0.06Ge0.94/Ge/Si layers is preserved also when a second, relaxed Ge layer is subsequently deposited. This makes the present reversegrading technique of direct interest also for achieving a low TDD in pure-Ge films.

The epitaxial integration of highly heterogeneous material systems with silicon (Si) is a central topic in (opto-)electronics owing to device applications. InP could open new avenues for the realization of novel devices such as high-mobility transistors in next-generation CMOS or efficient lasers in Si photonics circuitry. However, the InP/Si heteroepitaxy is highly challenging due to the lattice (∼8%), thermal expansion mismatch (∼84%), and the different lattice symmetries. Here, we demonstrate the growth of InP nanocrystals showing high structural quality and excellent optoelectronic properties on Si. Our CMOS-compatible innovative approach exploits the selective epitaxy of InP nanocrystals on Si nanometric seeds obtained by the opening of lattice-arranged Si nanotips embedded in a SiO matrix. A graphene/InP/Si-tip heterostructure was realized on obtained materials, revealing rectifying behavior and promising photodetection. This work presents a significant advance toward the monolithic integration of graphene/III-V based hybrid devices onto the mainstream Si technology platform.

In this paper we deposit structures comprising a stack of 10 periods made of 15-nm-thick Ge multiple quantum wells (MQWs) enclosed in a 15-nmthick Si 0.2 Ge 0.8 barrier on SiGe virtual substrates (VSs) featuring different Ge content in the 85%-100% range to investigate the influence of heteroepitaxial strain on Si 0.2 Ge 0.8 and Ge growth. With increasing Ge concentration of the VS, the growth rate of Si 0.2 Ge 0.8 in the MQWs increases. Si incorporation into the Si 0.2 Ge 0.8 layer also becomes slightly higher. However, almost no influence of the growth rate is observed for Ge growth in the MQWs. We argue that increased tensile strain promotes the Si reaction at the surface. In the case of Si 0.2 Ge 0.8 growth on Ge, we observe a smeared interface due to Ge segregation during the growth. Furthermore, we observe that the interface width increases with increasing Ge concentration of the VS. We attribute this observation to the increased segregation of Ge driven by increased strain energy accumulated in the Si 0.2 Ge 0.8 layers. We also observe that the MQW layer "filters out" threading dislocations formed in the VS.