Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, V FB , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density (D it ) from 8.55 × 10 11 to 1.09 × 10 12 cm −2 eV −1 is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.INDEX TERMS Germanium (Ge), heteroepitaxy, metal-oxide semiconductor (MOS) devices, silicon (Si), III-V materials.
The performance of thin-film GaN Schottky diodes fabricated using a large-area epitaxial lift-off (ELO) process is reported in this work. Comparison of the device characteristics before and after lift-off processing reveals that the Schottky barrier height remains unchanged by the liftoff processing and is consistent with expectations based on metal-semiconductor work function differences, with a barrier height of approximately 1 eV obtained for Ni/Au contacts on n− GaN. However, the leakage current in both reverse and low-forward-bias regimes is found to improve significantly after ELO processing. Likewise, the ideality factor of the Schottky diodes also improves after ELO processing, decreasing from n = 1.12–1.18 before ELO to n = 1.04–1.10 after ELO. A possible explanation for the performance improvement obtained for Schottky diodes after substrate removal by ELO processing is the elimination of leakage paths consisting of vertical leakage along threading dislocations coupled with lateral conduction through the underlying n+ buffer layer that is removed in the ELO process. Epitaxial liftoff with GaN may enable significant improvement in device performance and economics for GaN-based electronics and optoelectronics.
Carbon, a compensator in GaN, is an inherent part of the organometallic vapor phase epitaxy (OMVPE) environment due to the use of organometallic sources. In this study, the impact of growth conditions are explored on the incorporation of carbon in GaN prepared via OMVPE on pseudo-bulk GaN wafers (in several cases, identical growths were performed on GaN-on-Al2O3 templates for comparison purposes). Growth conditions with different growth efficiencies but identical ammonia molar flows, when normalized for growth rate, resulted in identical carbon incorporation. It is concluded that only trimethylgallium which contributes to growth of the GaN layer contributes to carbon incorporation. Carbon incorporation was found to decrease proportionally with increasing ammonia molar flow, when normalized for growth rate. Ammonia molar flow divided by growth rate is proposed as a reactor independent predictor of carbon incorporation as opposed to the often-reported input V/III ratio. A low carbon concentration of 7.3 × 1014 atoms/cm3 (prepared at a growth rate of 0.57 µm/h) was obtained by optimizing growth conditions for GaN grown on pseudo-bulk GaN substrates.
The current versus voltage (I-V) characteristics of a Ni/GaN Schottky diode are measured from 50 to 400 K and the temperature dependence of the extracted barrier heights and ideality factors is described as a consequence of lateral inhomogeneity at the metal-semiconductor (M-S) interface. It is shown that by invoking a modified log-normal distribution of barrier heights at the M-S interface, the extracted barrier height temperature dependence can be well explained. Further, it is shown that this approach can describe the voltage dependence of the lateral barrier distribution revealing that for effective barrier height values calculated at increasingly higher voltages, the distribution begins to converge on a single value of 0.77 eV. This value is in good agreement with the flat-band barrier height of 0.77±0.02 eV extracted from capacitancevoltage (C-V) measurements on the same device. The same procedure is used to describe the parallel conduction path apparent at low temperatures, revealing its behavior is indicative of an additional Schottky region with an increased density of low barriers which are more heavily perturbed by external bias. Finally, the model is successfully applied to previously published work on various Schottky diodes structures.
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