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A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

In this paper, we demonstrate the effect of dc substrate bias on high-rate deposition of microcrystalline silicon (μc-Si) films by using a high-density microwave plasma source. Film depositions are performed at a high silane concentration of 67% (deposition rate of ∼ 60 Å s−1) with a low substrate temperature of 250 °C. The μc-Si films deposited under appropriate negative dc substrate bias exhibit improved film crystallinity, mass density and reduced defect density along with thinner amorphous silicon incubation layer at the initial growth stage. These can be attributed to the beneficial effect of moderate ion bombardment as well as the less contribution of harmful short-lifetime radicals to film growth.

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Ultrahigh voltage SiC bipolar devices more than 13 kV were developed, and their package technology was investigated. As a result, we have succeeded in creating a 13kV level PiN diode without forward voltage degradation by using 4° off substrates and a 15kV p-channel IGBT with a low differential specific on-resistance (R diff,on ) at high temperature. Moreover, the results reveal that the nano-tech resin, improved resin and Si 3 N 4 DBC substrate are the best materials for package at high temperature and ultrahigh voltage.

We investigated the relationship between ion implantation-induced defects and electrical characteristics, especially focusing on the leak failure rate in SiC IEMOSs and PN diodes. It was found that dislocation exists in each leakage point by analyzing identical leak-failed IEMOS by emission microscopy and refraction X-ray topography. The leak failure rate of the PN diodes and IEMOS was improved with an increase in the ion implantation temperature under the implantation and annealing conditions used in this experiment. It is considered that ion implantation-induced defects lead to an increase in leak failure rates, and also enable a decrease in leak failure rates by raising the implantation temperature up to 600 deg.C.

We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (RonAactive) of 12 mW·cm2. The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.

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