An amorphous silicon field-effect phototransistor is fabricated using a processing technology compatible with conventional amorphous silicon-silicon nitride thin-film transistors. The phototransistor has an offset structure between the source and gate electrodes, where light is absorbed to produce a photocurrent. In an electron accumulation mode, the photocurrent is greater than the dark current by three orders of magnitude. In addition, the phototransistor is found to have output characteristics showing good saturation. Typical photoconductive gain of this saturation current is 17.

A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as. The formula is different from the conventional -sub model in that the exponent of is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical -sub model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.

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A ratio based hot-carrier degradation model for aged timing simulation of large CMOS circuits is presented. The model introduces gate-level representation and simply uses timing information.The proposed model is implemented in the prototype simulator in which the aged timing is obtained from the fresh timing and the precharacterized ratio. The simulated results show that the simulation can be performed at the size and speed of logic simulation with comparable accuracy of transistor-level simulator BTABERT.