A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

Abstract

A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as. The formula is different from the conventional -sub model in that the exponent of is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical -sub model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.

Effects of Negative Bias Temperature Stress-induced Degradation and Mismatch on pMOSFETs in 90 nm Technology

“…Early researches reported that pMOSFETs showed the worst degradation at DAHC and room temperature if cryogenic operation is unnecessary [1][2], but, based on 0.13 µm technology, our recent study showed that the worst case of HC has switched from DAHC to CHC and from low to high temperature. And the mechanisms pMOSFETs' degradation are related to bias temperature instability (BTI) effect plus reverse temperature effect [3][4].…”

Bit-Error-Rate Evaluation of Super-Resolution Near-Field Structure Read-Only Memory Discs with Semiconductive Material InSb

“…3,4) Additionally, owing to the activation energy provided by the recombination of electrons and holes, MOSFETs in the drain avalanche HC [DAHC -stressed at maximal substrate current I bm where V g ¼ ð1=3 {1=2ÞV d ] mode have traditionally been treated as the worst bias conditions. [5][6][7] Provided cryogenic operation is unnecessary, then the DAHC at room temperature constitutes the worst stress condition for testing the HC reliability of MOSFETs.…”

Effects of scaling on the impact ionization and sub‐threshold current in submicron MOSFETs

“…The aim of scaling is to reduce device dimensions without disturbing its performance. In the literature, different circuit and technological solutions have been proposed, to study the scaling effects in sub‐micron MOSFETs (Takeda et al ; 1982; Park et al , 1996; Iniguez and Fjeldly, 1997; Koike and Tatsuuma, 2002; Anil et al , 2003). Duncan et al (1998) studied the effects of various scaling techniques on hot carrier behavior in different kinds of n ‐channel MOSFET structures.…”