Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

Yonezawa, Hirokazu; Fang, Jingjun; Kawakami, Yoshiyuki; Iwanishi, N.; Wu, Lei; Chen, A.I.-H.; Koike, N.; Yeh, Chih‐Jung; Liu, Zhihong

doi:10.1109/iedm.1998.746287

Cited by 12 publications

(5 citation statements)

References 3 publications

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“…In addition, the authors provided systematic guidelines for the reliable design of inverter chains by using the parametric model they developed. In [35], the authors proposed a ratio-based hot-carrier degradation model for the agingaware timing simulation of large-scale circuits. The degraded circuit delay is expressed as a multiplicative factor of the original fresh delay.…”

Section: Hot-carrier Effectmentioning

confidence: 99%

A Leakage-Aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect

Kang¹,

Pedram²

2005

Journal of Low Power Electronics

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Leakage power and hot-carrier effects are emerging as key concerns in deep sub-micron CMOS technologies with respect to their effects on the total power dissipation and reliability of VLSI circuits. Leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small. Similarly, the hot-carrier effect is one of the most significant failure mechanisms in high-density VLSI circuits. In this paper, a technology mapping technique is presented for use in reducing the leakage power dissipation of the circuit by utilizing a dual-threshold voltage cell library and for minimizing the aged delay of the circuit by considering the effect of hot carriers on the cell speeds as the circuit ages. In addition, this paper presents two methods to reduce delay during technology mapping: primary output ordering and pin permutation. Experimental results show that the total power dissipation and leakage power dissipation can be reduced by up to 27% and 52% as a result of the leakage-aware technology mapping and that the circuit aging phenomenon can be reduced by up to 10.6% as a result of hot-carrier-aware technology mapping. Delay was also reduced by up to 13% using primary output ordering and pin permutation.

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Section: Hot-carrier Effectmentioning

confidence: 99%

A Leakage-Aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect

Kang¹,

Pedram²

2005

Journal of Low Power Electronics

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“…A probabilistic approach was proposed in [14] to estimate the degradation effects on timing. Recently, a ratio-based gate-level degradation model was proposed in [28] as a higher level abstraction. Each cell from the technology library is precharacterized for its degradation behavior under various stress conditions.…”

Section: Delay-constrained Reliability Optimizationmentioning

confidence: 99%

“…When the number of transistors in a series is , this equation can be generalized yielding (8). Based on this extended pin-to-pin delay model, full chip timing/reliability simulation is demonstrated to be 2 to 4 orders of magnitude faster [28], while accuracy is within 1% of the transistor-level counterpart.…”

Section: A Reliability Modelmentioning

confidence: 99%

Fast postplacement optimization using functional symmetries

Chang

Hsiao

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The timing-convergence problem arises because estimations made during logic synthesis may not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear-time algorithm is proposed to detect functional symmetries in the Boolean network which are then used as the basis for rewiring. Integration with an existing gate-sizing algorithm further proves the effectiveness of our technique. Three applications are demonstrated: delay, power, and reliability optimization.

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“…Therefore, a slow slew rate of input pins and a high load capacitance of an output pin of a gate will stress a transistor and a high switching activity in a gate will wear out the driving capability of a transistor quickly. In [15], authors proposed a ratio-based hot-carrier degradation model for the aging-aware timing simulation of large-scale circuits. The model utilized compact gatelevel representation with timing information only, rather than a conventional complex transistor-level approach.…”

Section: Hot-carrier Effectmentioning

confidence: 99%

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

Kang

Pedram

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

Cited by 12 publications

References 3 publications

A Leakage-Aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect

A Leakage-Aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect

Fast postplacement optimization using functional symmetries

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

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