A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si CbaMek. MotivationCarrier transport enhancement induced by strain has led to much interest in using strained Si to improve current drive in Si MOSFETs.

No abstract

No abstract

No abstract

The scaling limit of plasma enhanced chemical vapor deposited (PECVD) ultrathin(5-35 nm) silicon carbon nitride (SiCNH) dielectric as an oxidation and Cu diffusion barrier for damascene process is explored. The SiCNH cap's electrical properties, oxidation barrier performance, and the compositional depth profile analysis results showed that the scaling of the SiCNH cap is limited to 25 nm thickness. Without additional changes in current optimal SiCNH cap, 25 nm is the minimum required thickness for a reliable SiCNH cap in sub-30 nm Cu BEOL devices.

Thin SiN films deposited by plasma enhanced chemical vapor deposition (PECVD) have been analyzed by a variety of analytical techniques including Fourier Transform Infrared Spectroscopy (FTIR), X-ray reflectivity (XRR), and Rutherford Backscattering Spectrometry/Hydrogen Forward Scattering (RBS/HFS) to collect data on bonding, density and chemical composition respectively. Both tensile and compressive SiN films have been deposited and analyzed. Mechanisms of stress formation in SiN thin films are discussed. It has been found that amount of bonded hydrogen as detected by FTIR is higher for compressive films compared to tensile SiN films. Amount of bonded hydrogen in a film is correlated well with tensile stress. Effect of deposition temperature and other process parameters on stress have been studied. Exposure of SiN films to elevated temperature after deposition lead to increase in tension and degradation in compressive stress. New approaches to stress generation in thin films like creation of multilayer film structures have been delineated.

The fabrication of ultrathin strained silicon directly on insulator is demonstrated and the thermal stability of these films is investigated. Ultrathin (∼13 nm) strained silicon on insulator layers were fabricated by epitaxial growth of strained silicon on relaxed SiGe, wafer bonding, and an etch-back technique employing two etch-stop layers for improved across wafer thickness uniformity. Using 325 nm Raman spectroscopy, no strain relaxation is observed following rapid thermal annealing of these layers to temperatures as high as 950 °C. The thermal stability of these films is promising for the future fabrication of enhanced performance strained Si ultrathin body and double-gate metal-oxide-semiconductor field-effect transistors.

A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 μm), small critical dimension (1.5 μm), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer. The process also features thinning of the top wafer to 20 μm and a Cu backside BEOL on the thinned top wafer. The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems. Introduction3DI is a promising technology to further improve the performance of computational systems [1][2][3]. 3DI enables increased functions per physical die area, and can dramatically increase the available cache memory in multicore architectures. Previously, W TSVs for silicon carrier applications have been demonstrated with both high yield and reliability [4]. In addition, a hybrid metal/adhesive TJ process has been shown to be a highly reliable inter-chip connection process in multi-chip modules [5]. However, neither of these technologies has been demonstrated in a full integrated process on a 300-mm platform. In this paper, we utilize the combination of W TSVs and transfer-join assembly on 300-mm wafers, and demonstrate the functionality and robustness of this process.