Effect of rapid thermal annealing on strain in ultrathin strained silicon on insulator layers

Abstract

The fabrication of ultrathin strained silicon directly on insulator is demonstrated and the thermal stability of these films is investigated. Ultrathin (∼13 nm) strained silicon on insulator layers were fabricated by epitaxial growth of strained silicon on relaxed SiGe, wafer bonding, and an etch-back technique employing two etch-stop layers for improved across wafer thickness uniformity. Using 325 nm Raman spectroscopy, no strain relaxation is observed following rapid thermal annealing of these layers to temperatures as high as 950 °C. The thermal stability of these films is promising for the future fabrication of enhanced performance strained Si ultrathin body and double-gate metal-oxide-semiconductor field-effect transistors.

Growth of strained Si and strained Ge heterostructures on relaxed Si1−xGex by ultrahigh vacuum chemical vapor deposition

“…Another related application for ⑀-Si grown on Si-rich Si 1Ϫx Ge x is as an etchstop layer in the fabrication of SiGe or strained silicon-oninsulator substrates. 10,11 Wet-etching 6,10,11 or oxidation 12 of ⑀-Si demonstrates a high degree of selectivity with respect to Si 1Ϫx Ge x , allowing the transfer of thin uniform epitaxial films to oxidized handle wafers.…”

Non-contact, non-destructive characterization of Ge content and SiGe layer thickness using multi-wavelength Raman spectroscopy

“…In addition to the lack of availability of automatic handling of large size wafers, measurement accuracy, repeatability, spectral resolution, spatial resolution and calibration related issues have been preventing practical application of this technique from achieving wide acceptance as an in-line monitoring technique in the industry. Since the introduction of strain and Ge in Si for device performance enhancement, Raman spectroscopy has been revisited by many researchers as a preferred, non-destructive stress/strain characterization technique for semiconductor materials for the last few years [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20].…”

An efficient wet-cleaning of SiGe virtual substrates and of thick, pure Ge layers on Si(001) after a chemical mechanical planarization step

“…Such SiGe virtual substrates can be used as starting materials for the formation of SiGe-On-Insulator (SiGeOI) [1][2][3] or tensile-strained silicon on insulator (sSOI) [3][4][5][6] substrates. In a bulk form, they can serve as templates for the growth of tensile-strained Si surface channels with both high electron and hole mobilities (for Ge contents >30%) [7,8].…”