High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

Cheng, K.; Khakifirooz, A.; Loubet, N.; Luning, S.; Nagumo, T.; Vinet, M.; Liu, Q.; Reznicek, A.; Adam, Thomas; Naczas, Sebastian; Hashemi, Pouya; Kuss, J.; Li, J.; He, Hong; Edge, L. F.; Gimbert, J.; Khare, Prasanna; Zhu, Yu; Zhu, Zhengmao; Madan, A.; Klymko, N.; Holmes, Steven J.; Levin, T. M.; Hubbard, Alex; Johnson, R.C.; Terrizzi, M.; Teehan, S.; Upham, A.; Pfeiffer, G.; Wu, Tian-Li; Inada, A.; Allibert, F.; Nguyen, Bich‐Yen; Grenouillet, L.; Tiec, Y. Le; Wacquez, R.; Kleemeier, W.; Sampson, R.; Dennard, R.H.; Ning, T.H.; Khare, Mukesh; Shahidi, G.; Doris, B.

doi:10.1109/iedm.2012.6479063

Cited by 69 publications

(25 citation statements)

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“…The degradation of the intrinsic FinFET transistor performance should not be surprising due to diminishing effectiveness of strain and increase of parasitic resistance in highly scaled FinFET. Contrary to the common misconception, high performance FDSOI devices have been demonstrated by using intrinsically strained channels, i.e., tensily strained silicon for NFET and compressively strained SiGe for PFET [30,32,59]. As shown in Figures 10 and 11, at V DD = 0.9 V and I OFF = 100 nA/µm, I EFF is 820 µA/µm and 615 µA/µm for NFET and PFET, respectively.…”

Section: High Performance Fdsoimentioning

confidence: 99%

“…results in 250 mV V T reduction [32]. Therefore, one can use SiGe transistors for high performance (low V T ) applications such as critical logic path and use Si transistors channel for low leakage (high V T ) applications such as SRAM as shown in Figure 7.…”

Section: Multi-v T Options In Fdsoimentioning

confidence: 99%

“…FDSOI has been extensively studied and it is impossible to include all references in this paper. Besides FDSOI, other terminologies used in the literature to depict FDSOI include ultrathin body (UTB) [7-9], ultra-thin body and BOX (UTBB or UT2B) [13][14][15][16], silicon on thin BOX (SOTB) [17,18], ultra-thin SOI (UTSOI) [19][20][21][22], extremely thin SOI (ETSOI) [27][28][29][30][31][32][33][34], and depleted substrate transistor (DST) [35]. In textbook FDSOI transistor is defined as a transistor with a fully depleted channel in contrast to partially depleted SOI (PDSOI).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fully depleted SOI (FDSOI) technology

Cheng¹,

Khakifirooz

2016

Sci. China Inf. Sci.

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Section: High Performance Fdsoimentioning

confidence: 99%

Section: Multi-v T Options In Fdsoimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fully depleted SOI (FDSOI) technology

Cheng¹,

Khakifirooz

2016

Sci. China Inf. Sci.

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“…Ge enrichment has been used to generate SiGe on insulator samples and achieve thin compressive strained layer [3]. Ge enrichment starts with a thin oxide layer deposited to stabilize the surface of the SiGe layer, followed by a standard RTO process to oxidize the SiGe and push the Ge atoms in the SOI underneath yielding to 7nm SGOI containing a range of 15-35% Ge [4].…”

Section: B Sige On Utbb Fdsoimentioning

confidence: 99%

Silicon-Germanium (SiGe) composition and thickness determination via simultaneous smallspot XPS and XRF measurements

Lherron

Loubet

Liu

et al. 2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

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The thickness and composition determination of Silicon-Germanium (SiGe) films have been demonstrated using simultaneous X-ray Photoelectron (XPS) and X-ray Fluorescence (XRF) measurements. Measurements of SiGe films in various applications were explored. It is shown that the measurement is sensitive and linear over a much wider range of SiGe thickness, with excellent precision. Long term stability of the measurement is also shown to be very good.

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“…There are also reports of introducing SiGe at the 28nm node where the work function of the channel is modulated by adjusting the Ge concentration 60 . It is easier to introduce Ge into extremely thin (fully depleted) silicon on insulator structures through condensation of SiGe to form higher concentration Ge channel 61,62 . Such channels have demonstrated the lowest number of defects and have shown improved performance.…”

Section: Channel and Gate Engineeringmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

Cited by 69 publications

References 1 publication

Fully depleted SOI (FDSOI) technology

Fully depleted SOI (FDSOI) technology

Silicon-Germanium (SiGe) composition and thickness determination via simultaneous smallspot XPS and XRF measurements

Scaling Challenges for Advanced CMOS Devices

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