Summary The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO2 gives the best results for low power and high‐speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n‐CNTFET and varied for p‐CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N‐curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.

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This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around (GAA) MOSFETs. The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs, namely drain current (Id), transconductance to drain current ratio (gm/Id), Ion/Ioff, the cut-off frequency (fT) and the maximum frequency of oscillation (fMAX) are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator, ATLAS™. It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics (gm/Id, fT and fMAX) compared to the nanowire-based gate-all-around GAA MOSFETs. The silicon-nanotube MOSFET shows an improvement of ∼2.5 and 3 times in the case of fT and fMAX values respectively compared with the nanowire-based gate-all-around (GAA) MOSFET.

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The circuit changes the threshold voltage effectively with a definite delay and power by altering the body biasing of the transistors. The body bias is employed to govern the frequency and leakage of the memory device. The threshold voltage of individual transistor is decreases by applying the reverse body bias (RBB) and increases with forward body bias (FBB). This paper presents the viability of RBB to decrease the leakage power and increase in the speed of operations for SRAM circuit. The investigation of RBB dependencies on various performance parameters are analyzed. It is observed that the leakage power improves by 30.32% on applying RBB voltage compared to zero body bias while the transient power increases by 3.22% but decrease of delay by 84.56% dominates on it. Because of this the overall energy consumption reduces by 84.06%. Further the simulation work is carried out to see effect of supply voltage variation on leakage power at different RBB voltage and temperature. Therefore, the RBB scheme is beneficial for devices of low leakage, low energy and high speed of operation but this RBB voltage is limited by band-to-band tunneling current.