Performance evaluation of 6T, 7T &amp; 8T SRAM at 180 nm technology

Kumar, Mukesh; Ubhi, Jagpal Singh

doi:10.1109/icccnt.2017.8204092

Cited by 6 publications

(5 citation statements)

References 3 publications

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“…Table presents comparison for various metrics of different structures of SRAM memory cell. The result shows that the write ability of proposed 10T SRAM is 142.24%, 136.58%, and 61.81% higher than 6T SRAM, 10T SRAM, and Schmitt trigger (ST)‐based 10T SRAM, respectively. At the same time, the read stability is decreased.…”

Section: Stability Analysismentioning

confidence: 98%

“…In general, the silicon based MOSFET cell is very much delicate to temperature variations when contrasted with the CNTFET based memory cell . SRAM memory cell has many applications in modern computer systems like cache memory of the computer, laptop, A to D converter, high‐speed resistor, and electronics toys . CNTFET transistor can be effectively controlled by chirality, diameter, pitch, or number of tubes, as these are related to threshold voltage .…”

Section: Introductionmentioning

confidence: 99%

“…12 SRAM memory cell has many applications in modern computer systems like cache memory of the computer, laptop, A to D converter, high-speed resistor, and electronics toys. 13 CNTFET transistor can be effectively controlled by chirality, diameter, pitch, or number of tubes, as these are related to threshold voltage. 14 The energy bandgap of CNTFET is reciprocal to the diameter of tube.…”

Section: Introductionmentioning

confidence: 99%

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Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Kumar

Ubhi

2019

Circuit Theory & Apps

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Summary The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO2 gives the best results for low power and high‐speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n‐CNTFET and varied for p‐CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N‐curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.

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Section: Stability Analysismentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Kumar

Ubhi

2019

Circuit Theory & Apps

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“…The role of the bit line is transfer data of read and writes operation. There is no need for refreshing circuit in the SRAM cell [8]. An ideally SRAM cell is designed to be balanced device physically and electrically is perfectly between the two inverters.…”

Section: ░ 2 System Modelmentioning

confidence: 99%

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

Praveen

Singh²

2022

IJEER

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The growing markets for low-power electronic devices energized by battery have created the need for smaller power-efficient chips to prevent frequent charging of the source. Nowadays the market capitalization of low-power appliances is expected to grow from USD 4.9 billion by 2022 to USD 7.9 billion by 2027 as per global forecast to 2027 published by markets. The main factor leading to growth of low power electronics market includes demand of energy saving components, miniaturization, and entry of IoT (internet of things) devices. In addition, increased investment by automotive OEM (Original Equipment Manufacturer) and governments to promote the adoption of electric vehicles is expected to create more market opportunities. In this digital era, memory components play a major role in power consumption and this incites the research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology is growing rapidly towards greater integration into a single chip, resulting to a decrease in chip sizes using less space. Speed and stability demand is also growing up. Combined chip density increases as downtime technology continues. Stability and reliability are an important issue for the static random access memory (SRAM) memory device. In this paper, the design and analysis of CMOS based 9T SRAM cell in a variety of technologies is presented. The main focus of this review paper is to analyze 9T SRAM to test performance on several CMOS technologies (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with the help of a predictable technology (PTM) file. The butterfly curve method is used to examine the consistency of the SRAM bit cell in terms of static noise margin (SNM). It is clearly shown in this paper that as it progresses from 180nm to 14nm the delay decreases with stability.

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“…MuraliMohanBabu et al (2021) stated that the memory involves 70 to 80% area of processor that means it takes much more space and affects the performance and power consumption. The SRAM cell has an advantage that it does not require refresh operation periodically until the power is on (Kumar and Ubhi, 2017). Memory cell design concerns are critical for a variety of reasons.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of SRAM Cell for Smart Application

Praveen¹,

Singh²

2022

Journal of Computer Science

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In today's circuit technology, power consumption and savings are key concerns. The driving reasons behind these innovations are portable devices that require high throughput and low power dissipation, such as computers, phones, and Personal Digital Assistants (PDAs). In portable devices, reducing or decreasing IC dissipated power through design optimization is a big problem, and restricted battery lifespan places very severe restrictions on overall power usage. In this study SRAM circuit for smart applications has been investigated using various factors such as write, read, dynamic, static power with voltage and temperature. The power consumption analysis is the most essential criteria for memory design. Because data stability is a critical concern, affecting both the read and write operations. The implemented 9T SRAM in this study is more efficient than the other SRAM in terms of power usage. When compared with the existing SRAM circuits taken for comparison of different parameters, the proposed 9T SRAM, circuit uses less than 28.2% write power, while it uses about the same for read operation. The data retention voltage for both circuits is 0.29 V, which is utilized to store the data in the circuit. The 32 nm Bulk CMOS process technology from PTM files is used for designing and analysis.

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Performance evaluation of 6T, 7T & 8T SRAM at 180 nm technology

Cited by 6 publications

References 3 publications

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

Design and Analysis of SRAM Cell for Smart Application

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