Design and Analysis of SRAM Cell for Smart Application 

Abstract

In today's circuit technology, power consumption and savings are key concerns. The driving reasons behind these innovations are portable devices that require high throughput and low power dissipation, such as computers, phones, and Personal Digital Assistants (PDAs). In portable devices, reducing or decreasing IC dissipated power through design optimization is a big problem, and restricted battery lifespan places very severe restrictions on overall power usage. In this study SRAM circuit for smart applications has been investigated using various factors such as write, read, dynamic, static power with voltage and temperature. The power consumption analysis is the most essential criteria for memory design. Because data stability is a critical concern, affecting both the read and write operations. The implemented 9T SRAM in this study is more efficient than the other SRAM in terms of power usage. When compared with the existing SRAM circuits taken for comparison of different parameters, the proposed 9T SRAM, circuit uses less than 28.2% write power, while it uses about the same for read operation. The data retention voltage for both circuits is 0.29 V, which is utilized to store the data in the circuit. The 32 nm Bulk CMOS process technology from PTM files is used for designing and analysis.