Total ionizing dose hardness analysis of transistors in commercial 180 nm CMOS technology

Kumar, Mukesh; Ubhi, Jagpal Singh; Basra, Sanjeev; Chawla, Anuj; Jatana, H. S.

doi:10.1016/j.mejo.2021.105182

Cited by 12 publications

(1 citation statement)

References 15 publications

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“…When constructing CMOS logic circuits in sub-micron processes, p-MOSFETs are unaffected by TID effects. However, n-MOSFETs experience TID effects and generate trapped charges in the shallow trench isolation (STI) oxide, leading to leakage currents [7]. Recently, significant research has been conducted on layout modification techniques targeting n-MOSFETs, which are particularly susceptible to TID effects.…”

Section: Introductionmentioning

confidence: 99%

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

Ki,

Lee,

Lee

et al. 2023

Electronics

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This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility. Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the TID effect was validated through experiments.

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Section: Introductionmentioning

confidence: 99%