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History has shown that DRAM technology shrinks as the server memory density grows and, at the same time, user expectation of system uptime increases. Given this, new mitigation techniques will be required to reduce the impact of DRAM faults on server reliability, availability, and serviceability (RAS). This study shows the trade-offs in the effectiveness of two commonly used error correction codes (ECC) and two dynamic memory reconfiguration (DMR) schemes with various types of anticipated memory failures. This study proposes a "RAS intelligent" way to look at device reliability as DRAM technology scales below 100nm.

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The degradation mechanisms of both negative bias temperature instability ͑NBTI͒ and positive bias temperature instability ͑PBTI͒ were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation.