2008
DOI: 10.1109/ted.2008.2006543
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Characteristics of $\hbox{HfO}_{2}$ /Poly-Si Interfacial Layer on CMOS LTPS-TFTs With $\hbox{HfO}_{2}$ Gate Dielectric and $\hbox{O}_{2}$ Plasma Surface Treatment

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Cited by 19 publications
(14 citation statements)
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“…The fabrication process of Si-based TFTs is high compatible with VLSI technology and widely studied to achieve high performance characteristics for the realization of system-on-panel (SOP) [6], [7] and 3-D integrated circuits (3-D-ICs) [8], [9]. Low-temperature poly-Si (LTPS) TFTs with high-κ gate dielectric become a good candidate for the purposes of SOP and 3-D-ICs [10]- [13]. Because the poly-Si has much higher field effect mobility μ FE of electron and hole and driving current I drv than the amorphous-Si, and the high-κ gate dielectric can have much higher gate capacitance density to induce more inversion carriers with Manuscript smaller gate voltage, resulting in smaller threshold voltage (V TH ) and better subthreshold swing (SS) without any defect passivation process [10]- [13].…”
Section: Introductionmentioning
confidence: 99%
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“…The fabrication process of Si-based TFTs is high compatible with VLSI technology and widely studied to achieve high performance characteristics for the realization of system-on-panel (SOP) [6], [7] and 3-D integrated circuits (3-D-ICs) [8], [9]. Low-temperature poly-Si (LTPS) TFTs with high-κ gate dielectric become a good candidate for the purposes of SOP and 3-D-ICs [10]- [13]. Because the poly-Si has much higher field effect mobility μ FE of electron and hole and driving current I drv than the amorphous-Si, and the high-κ gate dielectric can have much higher gate capacitance density to induce more inversion carriers with Manuscript smaller gate voltage, resulting in smaller threshold voltage (V TH ) and better subthreshold swing (SS) without any defect passivation process [10]- [13].…”
Section: Introductionmentioning
confidence: 99%
“…Low-temperature poly-Si (LTPS) TFTs with high-κ gate dielectric become a good candidate for the purposes of SOP and 3-D-ICs [10]- [13]. Because the poly-Si has much higher field effect mobility μ FE of electron and hole and driving current I drv than the amorphous-Si, and the high-κ gate dielectric can have much higher gate capacitance density to induce more inversion carriers with Manuscript smaller gate voltage, resulting in smaller threshold voltage (V TH ) and better subthreshold swing (SS) without any defect passivation process [10]- [13]. In addition, the native growth interfacial layer (NIL) between high-κ gate dielectric and poly-Si channel can also terminate the dangling bonds of high-κ/ poly-Si interface to reduce the tail states of interface defect, resulting in the improvement of electron and hole μ FE [10]- [13].…”
Section: Introductionmentioning
confidence: 99%
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