No abstract

No abstract

No abstract

The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-ofthe-art CMOS process technology.