New Test Structure to Monitor Contact-to-Poly Leakage in Sub-90 nm CMOS Technologies

King, M.C.; Chin, Albert

doi:10.1109/tsm.2008.2000267

Cited by 3 publications

(3 citation statements)

References 11 publications

(2 reference statements)

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“…Starting at 65 nm technology, the poly-to-contact parasitic capacitance had the largest contribution among all of the parasitic capacitance components [21]. In addition, any direct short or higher leakage between the gate and the S/D terminals resulted in significant degradation of the yield [27]. From a process point of view, the taper profile of the contact may have a marginal distance from the top of the gate.…”

Section: Distance Of S/d Contact To Related Gate (Csd1)mentioning

confidence: 99%

“…To effectively monitor the leakage current between the contact and gate electrodes, it was proposed to block the extension implant (during the mask generation by modifying the Boolean operation) at this monitor structure [27]. This eliminates any interference with the gate leakage through the extension doping inside the AA, as most of the voltage is supported by the depletion region under the spacer, even at low drain voltages.…”

Section: Distance Of S/d Contact To Related Gate (Csd1)mentioning

confidence: 99%

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Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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Section: Distance Of S/d Contact To Related Gate (Csd1)mentioning

confidence: 99%

Section: Distance Of S/d Contact To Related Gate (Csd1)mentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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“…Process improvement for this rule for leakage reduction result mostly from contact etches profile optimization and some selective OPC. A special test chip was proposed for monitoring CS.D.1 leakage levels [17]. Comparison among several vendors of standard cells using "ranking methodology" was presented in [18].…”

Section: Csd1/2mentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

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Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed

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Prediction of ppm level electrical failure by using physical variation analysis

et al. 2016

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New Test Structure to Monitor Contact-to-Poly Leakage in Sub-90 nm CMOS Technologies

Cited by 3 publications

References 11 publications

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Prediction of ppm level electrical failure by using physical variation analysis

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