An efficient method is presented to model the parasitic three-dimensional (3-D) capacitance of VLSI multilevel interconnections. Based on the boundary-finite-element method (BFEM) of integral formulation, arbitrary triangle elements on the surface of conductors for charge distribution are used to efficiently calculate capacitances of both parallel conductors and complicated configurations such as crossing lines, corners, contacts, and their combinations. Using an adaptive multilevel Green's function and low-order polynomials as shape function, we apply the Galerkin principle over finite elements, and most of the surface integrals of charge distribution can be evaluated analytically and the singular integrals can be eliminated by choosing proper coordinate transformation. Moreover, an even less complex and more general method for arbitrary geometry configuration of multilevel interconnection lines is proposed in order to link with the finite element pre-processor in present CAD tools.
Process capability indices have been widely used in manufacturing industries to provide numerical measures of process potential and performance. In in-plant applications, some inevitable process mean shift may be undetected when the statistical process control charts are applied, particularly, in the bumping process for square bumps. Bothe in 2002 provided a statistical reason for considering such a shift in the process mean to accommodate the undetected mean shifts for normally distributed processes when evaluating process capability. In this paper, we consider a bumping process for square bumps in which the data can be formulated as a non-central chi-square distribution, a class of non-normal distributions. To evaluate the popular yield-based process capability Cpk more accurately, we accommodate the magnitudes of undetected mean shifts using the modified capability evaluation formula and tabulate the detection powers under various subgroup sizes and non-central chi-square parameters. Based on the modified process capability evaluation, we can provide a more reliable process capability evaluation of capability index Cpk for square bumps and make more correct decisions. For illustration purpose, a real application in a bumping factory which is located on the Science-based Industrial Park in Hsinchu, Taiwan, is presented.
An efficient method is presented to model the transient characteristics of distributed resistor-capacitor of ULSI multilevel interconnections on complex topography, in which the reformulation of the boundary-element method (BEM) and the Padè-via-Lanczos (PVL) algorithm associated with multilayer Green's function can avoid the redundant works on both volume mesh and transient analysis associated with the finite-difference method. An adaptive multilayer Green's function is adopted to investigate several cases that have revealed interesting physical mechanisms in charge transfer between conductors on multilayer topography. To improve the timing analysis efficiency of the finite-difference method, the dominant poles are obtained by introducing the PVL algorithm for model-order reduction. Hence, it is easy to calculate the transient characteristics of both parallel conductors and complicated configurations such as crossing lines, corners, contacts, multilayers, and their combinations.
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