A novel modeling technique for efficiently computing 3-D capacitances of VLSI multilevel interconnections-BFEM

Abstract

An efficient method is presented to model the parasitic three-dimensional (3-D) capacitance of VLSI multilevel interconnections. Based on the boundary-finite-element method (BFEM) of integral formulation, arbitrary triangle elements on the surface of conductors for charge distribution are used to efficiently calculate capacitances of both parallel conductors and complicated configurations such as crossing lines, corners, contacts, and their combinations. Using an adaptive multilevel Green's function and low-order polynomials as shape function, we apply the Galerkin principle over finite elements, and most of the surface integrals of charge distribution can be evaluated analytically and the singular integrals can be eliminated by choosing proper coordinate transformation. Moreover, an even less complex and more general method for arbitrary geometry configuration of multilevel interconnection lines is proposed in order to link with the finite element pre-processor in present CAD tools.