Reliability Mechanisms of LTPS-TFT With $\hbox{HfO}_{2}$ Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress

Ma, Ming-Wen; Chen, Chih-Yang; Wu, Woei-Cherng; Su, Chun-Jung; Kao, Kuo-Hsing; Chao, Tien−Sheng; Lei, Tan Fu

doi:10.1109/ted.2008.919710

Cited by 49 publications

(16 citation statements)

References 27 publications

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“…The S.S. degradation and I min increase of n-type LTPS-TFTs after PBTI as shown in Fig. 1 indicates the defect generation of both HfO 2 /poly-Si interface and poly-Si channel film [19,22]. Therefore, the mechanism of PBTI is that the channel electrons are accelerated by the gate voltage to collide with the weak bond of poly-Si and HfO 2 /poly-Si interface and then inject into the HfO 2 , resulting in the generation of oxide charge, interface trap state and poly-Si damage [22].…”

Section: Resultsmentioning

confidence: 94%

“…1. The degradation of subthreshold swing S.S. is attributed to the generation of the interface trap states N it of HfO 2 /poly-Si [15][16][17][18][19], which both NBTI and PBTI could degrade the HfO 2 /polySi interface. In addition, the increase of threshold voltage |DV TH | can be attributed to not only the degradation of subthreshold swing S.S. but also the oxide charge trapping in HfO 2 [19].…”

Section: Resultsmentioning

confidence: 99%

“…The degradation of subthreshold swing S.S. is attributed to the generation of the interface trap states N it of HfO 2 /poly-Si [15][16][17][18][19], which both NBTI and PBTI could degrade the HfO 2 /polySi interface. In addition, the increase of threshold voltage |DV TH | can be attributed to not only the degradation of subthreshold swing S.S. but also the oxide charge trapping in HfO 2 [19]. The flatband voltage shift |DV FB | of the LTPS-TFTs with undoped poly-Si channel can be used to monitor the threshold voltage shift |DV TH | by the oxide charge trapping, which the flatband voltage V FB is defined as the gate voltage yielding the minimum drain current from the transfer characteristics I D -V G curve [16].…”

Section: Resultsmentioning

confidence: 99%

“…Higher temperature of PBTI for n-type device shows more transconductance G m degradation and later saturation time of G m degradation, and the NBTI of p-type device shows much enhanced degradation rate with the increased temperature. The transconductance G m of polySi TFTs is strongly related to the tail-trap states located near the band edge of poly-Si in the HfO 2 /poly-Si interface and the grain boundaries of poly-Si near the surface conduction channel [16][17][18][19]. The saturated G m degradation of PBTI of n-type device indicates the generation of tail-trap states near the conduction band by PBTI is saturated, and the continuous G m degradation of NBTI for p-type device indicates the generation of tail-trap states near the valence band by NBTI is enhanced.…”

Section: Resultsmentioning

confidence: 99%

“…The saturated G m degradation of PBTI of n-type device indicates the generation of tail-trap states near the conduction band by PBTI is saturated, and the continuous G m degradation of NBTI for p-type device indicates the generation of tail-trap states near the valence band by NBTI is enhanced. In addition, the subthreshold swing S.S. of poly-Si TFTs is strongly related to the deep-trap states located near the midgap of poly-Si in the HfO 2 /poly-Si interface and the grain boundaries of poly-Si near the surface conduction channel [16][17][18][19]. Although the transconductance G m degradation of PBTI for n-type device shows a saturated behavior, the subthreshold swing S.S. degradation of PBTI doesn't, which is shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

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Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

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Section: Resultsmentioning

confidence: 94%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

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Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

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A Stacked p‐Type Low‐Temperature Polycrystalline Silicon Thin‐Film Transistor for Future Display Applications

Wang

Tai

Chang

et al. 2022

Adv Materials Technologies

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In this study, a novel structural design of the p‐type low‐temperature polycrystalline silicon thin‐film transistors (p‐type LTPS TFTs) applied to the pixel structure of displays is proposed. Compared to the conventional pixel structure of displays, the proposed architecture can achieve the aperture ratio improvement by stacking the switch thin‐film transistor and the storage capacitor in a pixel region to enlarge the active space. Therefore, the demands of high‐resolution characteristics, such as a high aperture ratio, and high pixel densities for high‐end displays or novel technologies, can be satisfied by the adoption of the proposed design concept. Furthermore, the discussion of experimental and simulated results in terms of device physics of the transistor indicates that proposed TFTs possess higher performance and reliability properties. By modulating the geometry of the drain‐connected bottom metal in stacked TFTs, output characteristics and hot carrier phenomenon in devices can be further improved. Time‐dependent transfer characteristics, extracted electrical parameters, and numerical simulation results are performed to support our design.

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Reduction of Parasitic Capacitance in Indium‐Gallium‐Zinc Oxide (a‐IGZO) Thin‐Film Transistors (TFTs) without Scarifying Drain Currents by Using Stripe‐Patterned Source/Drain Electrodes

Lee

Chen

Jeon

et al. 2018

Adv Elect Materials

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A new device structure of oxide thin‐film transistor (TFT) having lower overlap capacitance without scarifying the drain current is proposed. This can be used for high‐speed circuits and high frame rate displays using the conventional TFT manufacturing process. The existence of spreading currents in amorphous indium‐gallium‐zinc oxide (a‐IGZO) TFTs with stripe‐patterned source/drain (S/D) electrodes is demonstrated. The device performances of the a‐IGZO TFTs with various widths of stripe‐patterned S/D electrodes and open spaces between them are compared. The drain currents of the a‐IGZO TFTs are almost same when the width of open space changes from 0 to 10 µm because of the existence of spreading currents. The overlap capacitance between gate and S/D of the a‐IGZO TFTs can be significantly reduced without scarifying drain currents by using stripe‐patterned S/D electrodes. The operation frequency of the ring oscillator made of the TFTs with stripe S/D electrodes with 10 µm open space width is 2.5 times that made of the conventional a‐IGZO TFTs. This spreading current concept can be widely used for the design of oxide TFT array with low RC (resistance capacitance product) delay for high‐speed circuits.

show abstract

Reliability Mechanisms of LTPS-TFT With $\hbox{HfO}_{2}$ Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress

Cited by 49 publications

References 27 publications

Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

A Stacked p‐Type Low‐Temperature Polycrystalline Silicon Thin‐Film Transistor for Future Display Applications

Reduction of Parasitic Capacitance in Indium‐Gallium‐Zinc Oxide (a‐IGZO) Thin‐Film Transistors (TFTs) without Scarifying Drain Currents by Using Stripe‐Patterned Source/Drain Electrodes

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