Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

Cheng-Yu, William; Huang, Chih-Hsin

doi:10.1016/j.sse.2015.09.009

Cited by 10 publications

(4 citation statements)

References 23 publications

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“…The degradation of FeTFT's SS with the increase in PRG/ERS cycles is attributed to the application of V PRG /V ERS , causing electrical stress damage to the FeTFT and creating lattice defects and trap states on the poly-Si channel and surface of the FeTFT. [20][21][22][23] Ultimately, after 10 5 PRG/ERS cycles, the SS of the ERS-state degrades from 0.297 V/decade to 0.768 V/decade. In Fig.…”

Section: Resultsmentioning

confidence: 99%

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

Ma,

Su,

Kao

et al. 2024

ECS J. Solid State Sci. Technol.

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This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode's MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device's threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode's 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

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Section: Resultsmentioning

confidence: 99%

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

Ma,

Su,

Kao

et al. 2024

ECS J. Solid State Sci. Technol.

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“…It is apparent that the V TH of the poly-Si IDG-NSH-TFT increases with stress time, and the I ON decreases with stress time. It is due to the strong vertical electric field stress of the PGS, which leads to lattice damage and trap state generation in the poly-Si channel and the SiO 2 /poly-Si interface, as well as electron injection into the TGOX and subsequent trapping by TGOX, [18][19][20] as shown in Fig. 8.…”

Section: Resultsmentioning

confidence: 99%

“…It is because the breakage damage caused by the interaction between Si-H bonds and accumulated holes at the poly-Si grain boundaries and BGOX/poly-Si interface during negative bias stress is more substantial than the lattice damage caused by positive gate bias stress. 18,19 Under negative gate bias stress, the breakage damage inflicted on poly-Si TFTs is due to the accumulated holes attracted by the negative gate bias. These holes react with the Si-H bonds in poly-Si, causing the Si-H bonds to break and subsequently produce silicon dangling bonds.…”

Section: Resultsmentioning

confidence: 99%

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

Ma,

Su,

Kao

et al. 2023

ECS J. Solid State Sci. Technol.

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A polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (~ 4 nm) was fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device's VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

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“…For poly-Si, the generated Si + could be interface Figure 2A, the flatband voltage shift|4V FB |of NBTI is observed which can be used to monitor the threshold voltage shift by hole trapping. 11 We suppose that the generated Si…”

Section: Resultsmentioning

confidence: 99%

Two‐stage degradation in n‐channel LTPS‐TFTs under negative and positive bias stresses

Guo

Yan

et al. 2020

J Soc Info Display

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Device degradation behaviors of n‐channel low‐temperature polycrystalline silicon thin film transistors under negative bias stress and positive bias stress were investigated. It was found that the threshold‐voltage has a two‐stage degradation, shifting to different direction with time. The mobility and the subthreshold swing SS both show a dependence on the stress time. It was determined that the interface trap states, the grain boundary trap states, and electron trapping together dominate the time‐dependent degradation behaviors. The trap is caused by the rupture of Si─H and Si─O bonds. A comprehensive model is proposed to explain the time‐dependent degradation behaviors clearly. In addition, after removing the stress, the recovery behaviors of threshold voltage Vth can be observed, which provide the evidence supporting the degradation model proposed.

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Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

Cited by 10 publications

References 23 publications

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

Two‐stage degradation in n‐channel LTPS‐TFTs under negative and positive bias stresses

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