Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

Abstract

A polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (~ 4 nm) was fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device's VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

“…This is due to the enhanced control of the channel potential by the gate voltage in DG mode measurements, which suppresses the degradation influence of lattice damage on the device's electrical characteristics. 16,17 Because the gate electrode, which applies the sweeping V G voltage in DG operation, has a larger surface area on the channel compared to the SG operation mode, the potential and carrier concentration inside the channel are more easily modulated by V G , resulting in a lower ΔSS in DG operation mode compared to SG mode. Therefore, after 10 5 PRG/ERS cycles, the SS of the ERS-state in DG mode degrades from 0.288 V/decade to 0.490 V/ decade.…”

“…[12][13][14][15] To address these issues and enhance the endurance of FeFET, this work presents ferroelectric thin-film transistors (FeTFTs) with an asymmetric dual-gate (DG) structure. The use of DG operation helps mitigate the degradation effects induced by electrical stress on the device, 16,17 thereby improving the memory endurance of FeTFT. Additionally, the DG structure incorporates different gate insulator materials for the top gate (TG) and back gate (BG), forming an asymmetric gate insulator layer.…”