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As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical design for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical design for manufacturability and reliability.

Through-Silicon Via (TSV) is a promising technology to reduce the length of interconnect in a three dimensional integrated circuit (3D-IC). However, the area overhead of TSV also poses a negative impact on a 3D-IC. Using too many TSVs will increase the die size and cancel out the benefit brought by TSV. Therefore, in this paper we will analyze the trade-off among wirelength and the number of TSVs with different TSV sizes. Since the number of TSVs is determined by placement, we also investigate how placement affects the wirelength and the number of TSVs. The experimental result shows that, in our study cases, the average maximum TSV area is 25.30% of the cell area. Beyond this value, virtually no wirelength reduction can be obtained. I. INTRODUCTIONThree dimensional integrated circuit (3D-IC) is a promising solution to the next generation of leading-edge electronic designs. Different from the conventional 2D technology which can only arrange all devices on a single chip, a 3D-IC is capable of stacking up multiple chips with each of them smaller than a 2D-IC. Thus, the form factor of a 3D-IC is significantly reduced, and the devices are packed more closely. The compactness of 3D-IC potentially shortens the interconnects and improves performance. Additionally, a 3D-IC is also a platform for realizing heterogeneous integration. Components made of different processes, such as digital circuits, flashes, DRAMs and radio frequency modules, can be fabricated on individual chips and stacked up. The key to achieving inter-chip communication in modern 3D-ICs is the through-silicon via (TSV) which is a metal micro-channel vertically penetrating through a silicon substrate. A TSV can be placed in any viable white space on a chip and directly links an inter-chip net. TSV is able to remarkably reduce the signal delay and becomes the mainstream of 3D interconnection technology conceivably.Recently, 3D-IC has drawn much attention and been studied from many perspectives including fabrication processes [1], [2], production cost [3], yield rate [4], and thermal issues [5]- [7]. Prior research found that interconnects are significantly reduced with the existence of vertical connections. However, in the rudimentary analysis, the authors [8]-[12] viewed the vertical connections as volumeless objects and did not consider achievable size of TSV in present technology. Therefore, the result is over-optimistic. Although TSV is able to provide the highest density of inter-chip connections, area occupied by TSVs still cannot be ignored. In reality, applying too many TSVs significantly increases the chip size and extends the lengths of interconnects. Therefore, using more TSVs does not necessarily favor the performance of a design. On the contrary, minimizing the number of TSVs diminishes the benefit brought by TSV. Recently, there is plenty of literature discussing how wirelength varies with the number of TSVs. Most of their conclusions are drawn without considering the area of TSVs. Among them, only D. H. Kim et al. [13], [14] have studied th...

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In this paper, we will study fixed-outline floorplan ning in 3D-IC. Although there is abundant literature on 3D-IC floorplanning, none of them consider the areas and positions of signal through-silicon vias (TSVs). In previous research, TSVs are viewed as points during the floorplanning stage. Ignoring the areas, positions and connections of TSVs, previous research plans TSVs dispersively and estimates the wirelength by measuring the bounding box of pins in a net only. Moreover, although thermal issue is critical, there is a trade-off between wirelength and maximum temperature. Aggressively reducing the temperature may sacrifice the wirelength and impact the performance. There fore, in this paper, we will propose a 3D floorplaning algorithm which simultaneously plans hard macros and TSV-blocks to minimize the wirelength and the maximum on-chip temperature.Experimental results show that our algorithm achieves high successful rate. Compared to the average wirelength of a post processing TSV planning algorithm, our result is shorter by 22.3%. In addition, we also compare our algorithm to a 3D fixed outline floorplanner without considering thermal issue. The result shows that, our algorithm effectively reduces the maximum on chip temperature by 45% at the expense of 3.9% increase in wirelength.