We present in this article a new approach to the synthesis problem for finite state machines with the reduction of power dissipation as a design objective. A finite state machine is decomposed into a number of coupled submachines. Most of the time, only one of the submachines will be activated which, consequently, could lead to substantial savings in power consumption. The key steps in our approach are: (1) decomposition of a finite state machine into submachines so that there is a high probability that state transitions will be confined to the smaller of the submachines most of the time, and (2) synthesis of the coupled submachines to optimize the logic circuits. Experimental results confirmed that our approach produced very good results (in particular, for finite state machines with a large number of states).

In this article, we investigate compiler transformation techniques regarding the problem of scheduling VLIW instructions aimed at reducing power consumption of VLIW architectures in the instruction bus. The problem can be categorized into two types: horizontal scheduling and vertical scheduling. For the case of horizontal scheduling, we propose a bipartite-matching scheme for instruction scheduling. We prove that our greedy bipartite-matching scheme always gives the optimal switching activities of the instruction bus for given VLIW instruction scheduling policies. For the case of vertical scheduling, we prove that the problem is NP-hard, and we further propose a heuristic algorithm to solve the problem. Our experiment is performed on Alpha-based VLIW architectures and an ATOM simulator, and the compiler incorporated in our proposed schemes is implemented based on SUIF and MachSUIF. Experimental results of horizontal scheduling optimization show an average 13.30% reduction with four-way issue architecture and an average 20.15% reduction with eight-way issue architecture for transitional activities of the instruction bus as compared with conventional list scheduling for an extensive set of benchmarks. The additional reduction for transitional activities of the instruction bus from horizontal to vertical scheduling with window size four is around 4.57 to 10.42%, and the average is 7.66%. Similarly, the additional reduction with window size eight is from 6.99 to 15.25%, and the average is 10.55%.

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In this brief, a nonlinear digitalized modified logistic map-based pseudorandom number generator (DMLM-PRNG) is proposed for randomness enhancement. Two techniques, i.e., constant parameter selection and output sequence scrambling, are employed to reduce the computation cost without sacrificing the complexity of the output sequence. Statistical test results show that with only one multiplication, DMLM-PRNG passes all cases in SP800-22. Moreover, it passes most of the cases in Crush, one of the test suites of TesuU01. When compared with solutions based on digitized pseudochaotic maps previously proposed in the literature, in terms of randomness quality, our system is as good as a Rényi-map-based PRNG and better than a logisticmap-based PRNG. Moreover, compared with solutions based on a Rényi-map-based PRNG, DMLM-PRNG is better scalable to high digital resolutions with reasonable area overhead.Index Terms-Discrete chaos, logistic map, pseudorandom number generator (PRNG).

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In this paper, we propose a robust hyper-chaotic system that is suitable for digital securecommunication. The system consists of many coupled robust logistic maps that form a hyper-chaotic system. It has a higher degree of complexity than traditional discrete-time securecommunication systems that use only a single map. Moreover, the system has a very large parameter space which grows along with system precision. Hence, attacking the system by the method of map reconstruction in current computation technology is not feasible. Statistical analysis shows that the system achieves very high security level. Finally, two hardware architectures (multiple-cycle and pipelined) are proposed for area and performance optimization, respectively.

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Unused spare cells occur inevitably in traditional ECO design flow. It results in inefficient area usage, more leakage, and more IR drop impacts. To tackle these problems, a reconfigurable cell is proposed which serves the dual purposes of decoupling capacitance and spare cell in this paper. Before Engineering Change Order (ECO) is applied, these cells are pre-placed as decoupling capacitors. When ECO is applied, these cells are configured as functional cells. To demonstrate the efficiency of our configurable cell, we propose an algorithm for timing closure and IR drop minimization. Compared with traditional ECO flow, our method shows 16% reduction in maximum IR drop and 56% reduction in leakage before applying ECO, and 8% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, we show that there are less unsolved ECO timing paths left after applying our ECO timing optimization algorithm due to free selection of ECO gate type.