In this brief, a nonlinear digitalized modified logistic map-based pseudorandom number generator (DMLM-PRNG) is proposed for randomness enhancement. Two techniques, i.e., constant parameter selection and output sequence scrambling, are employed to reduce the computation cost without sacrificing the complexity of the output sequence. Statistical test results show that with only one multiplication, DMLM-PRNG passes all cases in SP800-22. Moreover, it passes most of the cases in Crush, one of the test suites of TesuU01. When compared with solutions based on digitized pseudochaotic maps previously proposed in the literature, in terms of randomness quality, our system is as good as a Rényi-map-based PRNG and better than a logisticmap-based PRNG. Moreover, compared with solutions based on a Rényi-map-based PRNG, DMLM-PRNG is better scalable to high digital resolutions with reasonable area overhead.Index Terms-Discrete chaos, logistic map, pseudorandom number generator (PRNG).
A nonlinear, Digitalized Modified-Logistic Map based Pseudo Random Number Generator (DMLM-PRNG) is proposed for randomness enhancement. We use parameter selection to reduce computation cost and output sequence scrambling to improve the quality or randomness. Statistical test results show that DMLM-PRNG passes all cases in SP800-22, and most of cases in Crush, one of the test suite of TesuU01. When compared to previous chaotic map based PRNGs, in terms of randomness quality, our system is as good as Addabbo's [1] combined system and better than Li's [2] system. Moreover, our system shows better scalability than Addabbo's system.
In this paper, we propose a technology mapping (11gorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase, based o n the results in [3], we propose a Look-Up-Table ( L U T ) based mapping algorithm. W e will take advantage of existing L U T mapping algorithms for area and depth minimization. Benchmark results show that our algorithm produce better results in terms of area and depth as compared to T E M P L A . '
To guarantee that an application-specific integrated circuit (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suffers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. However, the effectiveness of X-filling depends on the number and the characteristic of X-bit distribution. In this paper, we propose a physical-location-aware X-identification which redistributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X-filling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which redistributes X-bits evenly in all test vectors.Index Terms-At-speed scan test, automatic-test pattern generation (ATPG), IR-drop, X-filling, X-identification.
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