A technology mapping algorithm for CPLD architectures

Abstract

In this paper, we propose a technology mapping (11gorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase, based o n the results in [3], we propose a Look-Up-Table ( L U T ) based mapping algorithm. W e will take advantage of existing L U T mapping algorithms for area and depth minimization. Benchmark results show that our algorithm produce better results in terms of area and depth as compared to T E M P L A . '