Reliability analysis and improvement for multi-level non-volatile memories with soft information

Chen, Shih-Liang; Ke, Bo-Ru; Chen, Jiannan; Huang, Chih-Tsun

doi:10.1145/2024724.2024894

Cited by 12 publications

(7 citation statements)

References 5 publications

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“…However, the high-capacity flash memories suffer severe degradation of reliability and endurance due to higher error rate of MLC [1]. Recently, [2], [3] show the capabilities of using low-density parity-check (LDPC) codes as errorcorrecting codes (ECCs) to solve the reliability issues of NVMS. Compared to the conventional algebraic codes (e.g., BCH codes), LDPC codes provide much superior performance when the raw bit error rate (BER) is high in NVMS.…”

Section: Introductionmentioning

confidence: 99%

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Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems

Chung

Lin

Zhan

et al. 2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

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This paper presents a cost-effective scalable quasi-cyclic LDPC (QC-LDPC) decoder architecture for non-volatile memory systems (NVMS). A re-arranged architecture is proposed to eliminate the first-in-first-out (FIFO) memory in conventional decoders, where the FIFO size is linearly proportional to the codeword size. The area reduction is 18.5% compared to the conventional decoder architecture. The scalable datapaths of the proposed decoder reduce the re-design cost and enable the flexibility of using QC-LDPC codes for NVMS. A prototyping decoder with maximum codeword size of 9280 bits is implemented in TSMC 90nm CMOS technology, and the core area is only 2.52mm 2 at 138.8MHz.

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Section: Introductionmentioning

confidence: 99%

“…Contrary to the cases in advanced communication systems, there is no unified specification for QC-LDPC codes in NVMS. For example, QC-LDPC codes proposed in [2], [3] are very different in parameter setting. To reduce the re-design cost for different user-defined QC-LDPC codes in NVMS, a decoder with scalability is desirable.…”

Section: Introductionmentioning

confidence: 99%

Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems

Chung

Lin

Zhan

et al. 2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

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“…The continuous increasing demand for low-cost and high-density memory has driven the concept of multilevel cell (MLC) flash memory. [32][33][34][35][36][37][38] MLC technology allows the increment in the capacity of flash memory in a given area. [32][33][34][35][36][37][38] As compared to single-level cell, the bit density in flash memory can be doubled or tripled.…”

mentioning

confidence: 99%

“…[32][33][34][35][36][37][38] MLC technology allows the increment in the capacity of flash memory in a given area. [32][33][34][35][36][37][38] As compared to single-level cell, the bit density in flash memory can be doubled or tripled. The concept of dual charge storage layer MLC has been reported in Reference 23.…”

mentioning

confidence: 99%

“…34 Besides, MLC technology is more subject to various noises, which leads to degraded reliability performance. [32][33][34] To improve the functionality of the SONOS memory cell, self-amplification (SA) process, [39][40][41] and its application to store 3 bits has been demonstrated by the authors in Reference 40. While the reported results are promising, 40 the concept has been shown at longer L g ($1 μm), and the impact of gate length (L g ) scaling on the performance of MLC SONOS has not been reported yet.…”

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confidence: 99%

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Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

Bohara

Vishvakarma

2021

Int J Numerical Modelling

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This work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.

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