Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

Lin, Chung-Wei; Tsai, Ming-Chao; Lee, Kuang‐Yao; Chen, Tai-Chen; Wang, Ting-Chi; Chang, Yao-Wen

doi:10.1109/aspdac.2007.357992

Cited by 10 publications

(3 citation statements)

References 48 publications

(52 reference statements)

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“…Similarly, CMP topology is related to feature density [5,6,9,16]. To reduce the variation of post-CMP topology, we should reduce the variation of effective feature density between the tiles.…”

Section: H H H T Pd T Fd = +mentioning

confidence: 99%

“…Besides, multilevel routing system is easy to implement such a router with uniform objective because it can solve a problem at a global perspective and meanwhile handle it from all angles at each level. The layout topography is a global, long-range phenomenon [6], which should be handled not only in a global-routing tile but also among neighboring tiles, and not only Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Section: Figure 1 Profile After Ecp and Cmpmentioning

confidence: 99%

“…Inspired by the previous work, we consider that using ECP thickness range minimization as an objective during routing has a distinct advantage because the thickness variation can be predicted and optimized earlier. Furthermore, the post-CMP topology variation is highly correlated to the layout pattern density [5,6,9]. Managing wire density (both feature density and perimeter density) at the routing stage has great potential for final planarization of chip.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Full-chip routing system for reducing Cu CMP & ECP variation

Jia

Cai

Hong

2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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Topography variation has a significant impact on performance as well as printability for nanometer technologies. In this paper, we propose an improved full-chip routing system for reducing Cu CMP (Chemical Mechanical Polishing) & ECP (Electroplating) topology variation, in which CMP aware global routing, CMP aware layer assignment and ECP aware detailed routing are integrated. To the best of our knowledge, this is the first work to consider both Cu CMP and ECP variation all through routing procedure. First, a Cu CMP and ECP topology model considering both perimeter density and feature density is used in global routing, layer assignment and detailed routing to guide the whole optimization procedure. Second, a W-shape multilevel routing model is applied to fully control topology variation from a macroscopic level to a microscopic level. Third, layer assignment which plays a key role in trading off the density between interlayer and intralayer, is integrated into the multilevel routing system and a fast simulated annealing based algorithm is presented to take additive effect on multiple layers into consideration. Experiments show that the proposed algorithm can reduce 6%-7% post-ECP variation and 15%-17% post-CMP variation on average than CMP-aware detailed routing algorithm in [5]. Furthermore, it can insert smaller amount (about 5%) of dummy fill, which means less impact on performance.

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Section: H H H T Pd T Fd = +mentioning

confidence: 99%

Section: Figure 1 Profile After Ecp and Cmpmentioning

confidence: 99%