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Abstract-In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with a small number of adders and registers. The proposed method is an efficient way to reduce the function blocks using the horizontal and vertical CSE. The FIR filters were synthesized from Verilog HDL code. Area and critical path values were evaluated for 0.35 µm standard CMOS library. Compared with the previous CSE techniques, the presented approach can save from a minimum of 0.8% up to a maximum 21.5% of gate area. Also, the critical path of proposed method is an average of 3.2% or 17.6% shorter than those of the other methods.

Abstract:The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4 nW at best case and 109.8 nW at worst case, when AC signal and clock frequencies are 110 MHz and 10 MHz, respectively. Keywords:synchronization, adiabatic dynamic CMOS logic (ADCL), low power, ADCL buffer Classification: Integrated circuits

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This paper proposes a memristor SPICE model using the Tukey window (or tapered cosine window) function. Compared with the previously proposed models based on the boundary function, the proposed model is resistant to numerical errors. From the SPICE result of a relaxation oscillator, we observe that the proposed model can be effectively used to minimise the effect of round-off errors.

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In Sprague-Dawley rats kept under 14L:10D (lights on 05:00-19:00 h), parturition occurred during the light phase on Day 23, and the pre-partum decrease in progesterone concentrations was observed between 07:00 and 15:00 h during the light period on Day 22. When the rats were transferred to reversed light-dark regimen (lights on 17:00-07:00 h) on Day 7, the progesterone decrease and parturition still occurred during the light period on Day 21 and 22-23, respectively. However, when rats were kept in constant darkness from Day 7, parturition occurred independently of the time of day between Day 22 and 24. A gradual decline of progesterone concentrations was randomly observed in individual rats. In Wistar rats kept under the usual light-dark regimen, parturitions were biphasic, occurring during the light periods on Day 22 and 23. The progesterone decrease occurred at the usual time even when the lighting regimen was changed only on the day of the expected progesterone decrease. However, treatment with pentobarbitone sodium at 15:00, 19:00 or 21:00 h, but not at 12:00 or 23:00 h, on Day 21 resulted in a delay of progesterone decrease and of parturition. Complete lesion of the suprachiasmatic nucleus on Day 13 or 14 led to advancement and random distribution of the time of birth. These results suggest that the time of parturition and of pre-partum progesterone decrease may be closely associated with an endogenous circadian system, and a luteolytic factor involving the nervous system may be present during a limited period before parturition.

To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 μW and 58.1 μW at 3 kHz and 10 MHz, respectively.