Abstract:The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4 nW at best case and 109.8 nW at worst case, when AC signal and clock frequencies are 110 MHz and 10 MHz, respectively.
Keywords:synchronization, adiabatic dynamic CMOS logic (ADCL), low power, ADCL buffer Classification: Integrated circuits
The low mobility and large contact resistance in organic thin-film transistors (OTFTs) are the two major limiting factors in the development of high-performance organic logic circuits. Here, solution-processed high-performance OTFTs and circuits are reported with a polymeric gate dielectric and 6,6 bis (trans-4-butylcyclohexyl)-dinaphtho[2,1-b:2,1-f]thieno[3,2-b]thiophene (4H–21DNTT) for the organic semiconducting layer. By optimizing and controlling the fabrication conditions, a high saturation mobility of 8.8 cm2 V−1 s−1 was demonstrated as well as large on/off ratios (> 106) for relatively short channel lengths of 15 μm and an average carrier mobility of 10.5 cm2 V−1 s−1 for long channel length OTFTs (> 50 μm). The pseudo-CMOS inverter circuit with a channel length of 15 μm exhibited sharp switching characteristics with a high signal gain of 31.5 at a supply voltage of 20 V. In addition to the inverter circuit, NAND logic circuits were further investigated, which also exhibited remarkable logic characteristics, with a high gain, an operating frequency of 5 kHz, and a short propagation delay of 22.1 μs. The uniform and reproducible performance of 4H–21DNTT OTFTs show potential for large-area, low-cost real-world applications on industry-compatible bottom-contact substrates.
To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 μW and 58.1 μW at 3 kHz and 10 MHz, respectively.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.