To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 μW and 58.1 μW at 3 kHz and 10 MHz, respectively.
The environment development for deep sleep has been studied using analysis results of the big data about vital signs and parameters in the bedroom. The organic light emitting diode (OLED) illuminations of the bedroom are dimming using analysis results of the big data. Therefore, a low-power and compact design of dimming part is required for OLED illumination system. In this paper, the optimized control block of the clock cut-off circuit was designed using De Morgan's laws with adiabatic dynamic CMOS logic (ADCL) digital 3-bit pulse width modulation (PWM). The designed clock cut-off circuit pauses the D-flipflops (D-ffs) after cutting off the clock at both
We propose a design method of fast Fourier transform (FFT) large-scaled integration (LSI) for an orthogonal frequency division multiplexing (OFDM) system. The proposed FFT LSI is designed with simple current mode circuits, wired-OR connection and gate-width-ratioed current mirror. For a low power consumption, two design methods are proposed, current-cut (CC) and rounding process. The CC operation is performed with on-off operation of a current source. The rounding process is adopted for the component of the FFT matrix. Bit error rate (BER) in the OFDM system is simulated from “0.1” rounding step to “1.0”. The BER performance of the FFT matrix with the “0.2” rounding step has little degradation from that of the original FFT matrix. The 8-point FFT LSI with the “0.2” rounding step is designed and implemented using a 0.8 µm complementary metal-oxide semiconductor (CMOS) technology. On the basis of measurement of the 8-point FFT LSI, the power consumption of the 64-point FFT LSI using CC can be estimated as being less than 10 mW.
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