Design of the ultra low-power synchronizer using ADCL buffer for adiabatic logic

Abstract

Abstract:The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4 nW at best case and 109.8 nW at worst case, when AC signal and clock frequencies are 110 MHz and 10 MHz, respectively. Keywords:synchronization, adiabatic dynamic CMOS logic (ADCL), low power, ADCL buffer Classification: Integrated circuits

Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic

“…However, the power consumption of clock generators with proposed synchronization for only ADCL in Ref. [4] instead of a PLL or a DLL is lower than that of this work. Although, proposed clock generator has a demerit in way of power consumption it has more merits than individually designed types as shown in Fig.…”

“…The ADCL circuits consist of CMOS logic, AC power and two diodes to keep high and low levels [3,4]. An ADCL inverter gate is shown in Fig.…”

“…In particular, the adiabatic dynamic CMOS logic circuit (ADCL) achieves ultra low energy dissipation by restricting current to flow across devices with low voltage drop and by recycling the energy stored on their capacitors [3,4]. It is known that output voltage of the ADCL gates is synchronized with the power supply voltage.…”

“…In reference [4], a low-power synchronizer circuit was proposed using the designed ADCL buffer when an alternate current (AC) power supply and a clock generator are designed respectively. On the other hand, a low-power clock generator synchronized with the AC power signal is proposed for ADCL system using defined synchronization conditions and phase margin between clock and AC power by ADCL architecture in this paper.…”

“…A power dissipation is incurred by resistive component of logic circuit in the conventional CMOS logic, because this logic circuit uses a constant voltage; direct current (DC) power supply. In order to minimize the power dissipation, an adiabatic charging is one of promising candidates with AC power which has slower rising/falling time than charge/discharge time constant [1,2,3,4]. Figure 1 shows operations at a normal RC circuit with DC signal, adiabatic charging, and unsynchronization.…”