New Cost-effective VLSI Implementation of Multiplierless FIR Filter using Common Subexpression Elimination

Abstract

Abstract-In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with a small number of adders and registers. The proposed method is an efficient way to reduce the function blocks using the horizontal and vertical CSE. The FIR filters were synthesized from Verilog HDL code. Area and critical path values were evaluated for 0.35 µm standard CMOS library. Compared with the previous CSE techniques, the presented approach can save from a minimum of 0.8% up to a maximum 21.5% of gate area. Also, the critical path of proposed method is an average of 3.2% or 17.6% shorter than those of the other methods.

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

“…In Fig. 4, for Q(1, 2)= [10,8], we get R=2 and J=6. Hence, bit i=1 can make a subexpression with bit J=6.…”

“…Hence, additional LOs are required to implement the second half of the coefficients as symmetry cannot be exploited fully if VCSs are used for CSE. Hence, the hardware requirement and logical depth shown in [3], [8], and [10] are not sufficiently accurate [1]. The constraints discussed in this paper are not applicable to antisymmetric filters.…”

“…HCS elimination (HCSE) and VCS elimination (VCSE) can be combined to show better results than in [20]. In [8], the CSE method incorporating both VCSE and HCSE is shown to reduce the average area by 6.4% and 3.8% over the methods in [13] and [21], respectively .…”

“…By considering the implementation of the first half of the coefficients only, and assuming that the remaining half of the coefficients are symmetric to the first half so that their output can be shared, the authors in [3], [8], and [10], ignored the fact that VCSs put constraints on this sharing of output [1]. Hence, additional LOs are required to implement the second half of the coefficients as symmetry cannot be exploited fully if VCSs are used for CSE.…”

“…By searching the index of minimum Q in P, we search for a bit whose occurrences with bit 'i' is highest and lowest with any other bit in matrix B (see (8)). In Fig.…”