An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

Vinod, A. P.; Lai, Eseng; Maskell, Douglas L.; Meher, Pramod Kumar

doi:10.1016/j.vlsi.2009.07.001

Cited by 33 publications

(53 citation statements)

References 22 publications

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“…Hence, additional LOs are required to implement the second half of the coefficients as symmetry cannot be exploited fully if VCSs are used for CSE. Hence, the hardware requirement and logical depth shown in [3], [8], and [10] are not sufficiently accurate [1]. The constraints discussed in this paper are not applicable to antisymmetric filters.…”

Section: Existing Methodsmentioning

confidence: 93%

“…By considering the implementation of the first half of the coefficients only, and assuming that the remaining half of the coefficients are symmetric to the first half so that their output can be shared, the authors in [3], [8], and [10], ignored the fact that VCSs put constraints on this sharing of output [1]. Hence, additional LOs are required to implement the second half of the coefficients as symmetry cannot be exploited fully if VCSs are used for CSE.…”

Section: Existing Methodsmentioning

confidence: 99%

“…In [1], Vinod and others analyzed the impact of HCSE and VCSE in exploiting the symmetry of FIR coefficients. The authors demonstrated an optimization algorithm to reduce the LO and LD requirements.…”

Section: Comparisonmentioning

confidence: 99%

“…They claimed that the algorithm produced the best reduction in number of LOs compared to the best known algorithm in the literature without increasing the LD requirement. The results in [1] (in terms of LOs and LD) have been compared with several CSE methods, such as Hartley [4], Pasko [5], BHM [17], C1 algorithm [22], MAG [19], NR-SCSE [6], HCUB [18], CSDC [21], and CRA-2 [15], [9]. The authors in [1] also presented design examples of several FIR filters using the proposed common subexpression algorithm.…”

Section: Comparisonmentioning

confidence: 99%

“…We also use common subexpression elimination (CSE) to eliminate the redundant computations that exist in an MB by locating the most common bit patterns, called common subexpression (CS), existing in the binary representation of coefficients. Most authors have used canonical sign digit (CSD) representation to represent the coefficients [1]- [10]. In the CSD code of a number, each bit is set to 0, 1, or -1 so as to minimize the total number of nonzero An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter…”

Section: Introductionmentioning

confidence: 99%

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An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

Hassan¹

2011

ETRI J

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The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

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Section: Existing Methodsmentioning

confidence: 93%

Section: Existing Methodsmentioning

confidence: 99%

Section: Comparisonmentioning

confidence: 99%

Section: Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

Hassan¹

2011

ETRI J

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ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

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Bottlenecks in Finite Impulse Response Filter Architectures on a Reconfigurable Platform

Shinde

Vijaya

2021

Advances in Intelligent Systems and Computing

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An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

Cited by 33 publications

References 22 publications

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Bottlenecks in Finite Impulse Response Filter Architectures on a Reconfigurable Platform

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