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I AbstractWe discuss characteristics variance in detail, caused by probing stress in 28nm High-K and Metal Gate process. The V th variation of nch large size transistor increases by 20% comparnig with weak probing pressure( 0). Regarding small size transistors, probing stress impact both on V th fluctuation and on T pd fluctuation is small.Moreover, we extracted the space distribution of probing stress quantitatively. It is useful to calibrate a stress simulation methodology and to facilitate evaluation of the mechanical strength of the material. II IntroductionBecause of the demand for smaller chip size, active circuits under bonding/probing pads are becoming a general technology. Several reports have described the fluctuation of characteristics such as propagation delay and drain current caused by the bonding and probing stress[1] [2]. As described in this paper, we discuss transistor and propagation delay characteristic variance caused by probing stress in 28nm High-K and Metal Gate processes. The characteristic variance is compared directly with the local variation, which originates from dopant fluctuation. Results indicate whether probing stress should be examined at the time of circuit design stage.Moreover, the stress which reaches the silicon surface during probing test is extracted using an accurate physical model. The quantitative space distribution of stress is useful to calibrate a stress simulation methodology and to facilitate evaluation of the mechanical strength of the material. Figure 1 shows a schematic of the test structure layout for transistor characteristics. For detailed evaluation of the fluctuation of characteristics, an arrayed transistor circuit is placed under the probing pad. These transistors can be measured selectively and independently using a decoder circuit. The probing pad size is 50 µm × 50 µm, and transistors are arrayed in 30 µm × 30 µm area. The total transistor number is 128 in an array. The characteristic fluctuation, induced by probing stress, is extracted by changing the probing pressure mechanically. Local variation is extracted with weak probing pressure ( 0) conditions. Two types of gate length, minimum length, and 0.9 µm are included in an array. The number of 0.9 µm gate length transistors is nine. These are located at the center and corner uniformly in the array. The remaining number is the minimum gate length transistor. Three types of gate widths of minimum width, 0.135 µm and 0.27 µm are arranged at a separate array. Figure 2 presents a schematic of the test structure layout for propagation delay(T pd ). Four inverter ring oscillators are placed under the probing pad. These are measured independently. The gate length and gate width are, respectively, minimum, and 0.135 µm. Fig. 1: Layout schematic of transistors. These are located under the probing pad. III Test StructureFig. 2: Layout schematic of ring oscillators. Four ring oscillators are located under the probing pad.

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