Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction , to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor , a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.
The problem of sensitivity to errors in artificial neural networks is discussed here considering an abstract model of the network and the errors that can affect a neuron's computation. Feed-forward multilayered networks are considered; the performance taken into account with respect to error sensitivity is their classification capacity. The final aim is evaluation of the probability that a single neuron's error will sect both its own classification capacity and that of the whole network. A geometrical representation of the neural computation is adopted as the basis for such evaluation. Probability of error propagation is evaluated with respect to the single neuron's output as well as to the complete network's output. The information derived is used to evaluate, for a specific digital network architecture, the most critical sections of the implementation as far as reliability is concerned and thus to point out candidates for ad-hoc fault-tolerance policies.
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