Reconfigurable architectures for VLSI processing arrays

Sami, Mariagiovanna; Stefanelli, R.

doi:10.1109/proc.1986.13533

Cited by 148 publications

(31 citation statements)

References 11 publications

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“…We also developed efficient algorithms for reconfiguration in a neighborhood reconfiguration model (see also [CF90,SS86]). In this model, the neighborhood reconfiguration consists of an n x k rectangular array with one column of spare PEs on one side.…”

Section: New Resultsmentioning

confidence: 99%

Algorithms and Architectures for High Speed Signal Processing

Kailath¹,

Paulraj²

1990

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Section: New Resultsmentioning

confidence: 99%

Algorithms and Architectures for High Speed Signal Processing

Kailath¹,

Paulraj²

1990

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“…We propose a reconfiguration scheme where a mesh-connected highly parallel computer is divided into groups of PEs with small mesh-structures, a spare row is added to each group in the same way as in [2], these planes are successively connected upward and downward, and, finally, the top and bottom groups are connected. The scheme has such a feature that although switchings for reconfiguration are done locally, compensations are done globally, considering the distribution of faults over the whole plane.…”

Section: Introductionmentioning

confidence: 99%

Construction of fault‐tolerant mesh‐connected highly parallel computer and its performance analysis

Takanami

Inoue

Watanabe

et al. 1993

Systems & Computers in Japan

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SUMMARYA reconfiguration scheme is proposed in which a mesh-connected highly parallel computer is divided into groups of PEs with small mesh-structures, a spare row is added to each group (in what follows, such a group with a spare row is called a plane), these planes are successively connected upward and downward, and finally the top and bottom groups are connected. The scheme has such features that: (1) although switchings for reconfiguration are done locally, compensations are done globally, considering the distribution of faults over the whole planes; and (2) switching algorithm and circuits are simple and hence our scheme is suitable for dynamic reconfiguration.First, a method for repairing faults is described, and the necessary and sufficient condition for repairability is given. Next, formulas for the reliabilities of systems are given. Using these formulas, an example of computing the improvement degree of M'ITF is illustrated and the result is compared with those in the literature. The probabilities of system survivals against the number of faulty PE's also are analyzed and the results are compared with those in the literature. Finally, logic circuits for the reconfiguration are shown and the correctness of their behavior is proved.

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“…In Section 4, we show how ECCs can be used to form (intersecting) processor groups, and how the deterministic and average error detectability of an ECC form lower bounds for the deterministic and average fault tolerance of the corresponding FT multiprocessor, and, in general, why they are a good choice to determine these groupings. Some previous probabilistic methods [22], [26], [28] have also used intersecting processor groups for the special case of the 2D mesh topology; their processor groups are the rows and columns of the 2D mesh, and, thus, they fortuitously happen to be based on the 2D-parity code. In Section 8, we compare our designs to some of the best of such previous designs.…”

Section: Intersecting Ft Processor Groupsmentioning

confidence: 99%

“…Since such designs are geared toward having a large fault tolerance on the average (over all fault patterns), but the worst-case fault tolerance may be lower, we call them probabilistic FT designs. Such probabilistic designs have also been proposed previously, though mainly for 2D mesh-connected multiprocessors [6], [22], [26], [27], [28]. In contrast, in this paper, we develop probabilistic designs that are applicable to any topology, and, for the special case of the 2D mesh, we compare our resulting designs' reconfigurabilities and hardware overheads to those of the best previous probabilistic designs [6], [27], [28].…”

Section: Introductionmentioning

confidence: 96%

“…A number of researchers have proposed various design methods for structural fault tolerance in multiprocessors, for example, [2], [4], [5], [6], [7], [8], [10], [11], [12], [13], [14], [15], [19], [22], [23], [24], [25], [26], [27], [28]. Most of this work has dealt with the design of deterministic k-faulttolerant (k-FT) multiprocessors in which there are k or more spare processors, and the link and switch complexity is high enough to tolerate any k processor failures (but not more than k processor failures) [2], [4], [5], [6], [7], [8], [10], [11], [12], [13], [14], [15], [19], [27], [23], [24].…”

Section: Introductionmentioning

confidence: 99%

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Node covering, error correcting codes and multiprocessors with very high average fault tolerance

Dutt

Mahapatra

Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers

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Abstract-Structural fault tolerance (SFT)is the ability of a multiprocessor to reconfigure around faulty processors or links in order to preserve its original processor interconnection structure. In this paper, we focus on the design of SFT multiprocessors that have low switch and link overheads, but can tolerate a very large number of processor faults on the average. Most previous work has concentrated on deterministic k-fault-tolerant (k-FT) designs in which exactly k spare processors and some spare switches and links are added to construct multiprocessors that can tolerate any k processor faults. However, after k faults are reconfigured around, much of the extra links and switches can remain unutilized. It is possible within the basic node-covering framework, which was introduced by Dutt and Hayes as an efficient k-FT design method, to design FT multiprocessors that have the same amount of switches and links as, say, a two-FT deterministic design, but have s spare processors, where s ( 2, so that, on the average, k = Q(s) (k £ s) processor failures can be reconfigured around. Such designs utilize the spare link and switch capacity very efficiently, and are called probabilistic FT designs. An elegant and powerful method to construct covering graphs or CG's, which are key to obtaining the probabilistic FT designs, is to use linear error-correcting codes (ECCs). We show how to construct probabilistic designs with very high average fault tolerance but low wiring and switch overhead using ECCs like the 2D-parity, full-two, 3D-parity, and full-three codes. This design methodology is applicable to any multiprocessor interconnection topology and the resulting FT designs have the same node degree as the non-FT target topology. We also analyze the deterministic fault tolerance for these designs and develop efficient layout strategies for them. Finally, we compare the proposed probabilistic designs to some of the best deterministic and probabilistic designs proposed in the past, and show that our designs can meet a given mean-time-to-failure (MTTF) specification at much lower hardware costs (switch complexity, redundant wiring area, and spare-processor overhead) than previous designs. Further, for a given number of spare processors, our designs have close-to-optimal reconfigurabilities that are much better than those of previous probabilistic designs.

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Reconfigurable architectures for VLSI processing arrays

Cited by 148 publications

References 11 publications

Algorithms and Architectures for High Speed Signal Processing

Algorithms and Architectures for High Speed Signal Processing

Construction of fault‐tolerant mesh‐connected highly parallel computer and its performance analysis

Node covering, error correcting codes and multiprocessors with very high average fault tolerance

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