Node covering, error correcting codes and multiprocessors with very high average fault tolerance

Abstract

Abstract-Structural fault tolerance (SFT)is the ability of a multiprocessor to reconfigure around faulty processors or links in order to preserve its original processor interconnection structure. In this paper, we focus on the design of SFT multiprocessors that have low switch and link overheads, but can tolerate a very large number of processor faults on the average. Most previous work has concentrated on deterministic k-fault-tolerant (k-FT) designs in which exactly k spare processors and some spare switches and links are added to construct multiprocessors that can tolerate any k processor faults. However, after k faults are reconfigured around, much of the extra links and switches can remain unutilized. It is possible within the basic node-covering framework, which was introduced by Dutt and Hayes as an efficient k-FT design method, to design FT multiprocessors that have the same amount of switches and links as, say, a two-FT deterministic design, but have s spare processors, where s ( 2, so that, on the average, k = Q(s) (k £ s) processor failures can be reconfigured around. Such designs utilize the spare link and switch capacity very efficiently, and are called probabilistic FT designs. An elegant and powerful method to construct covering graphs or CG's, which are key to obtaining the probabilistic FT designs, is to use linear error-correcting codes (ECCs). We show how to construct probabilistic designs with very high average fault tolerance but low wiring and switch overhead using ECCs like the 2D-parity, full-two, 3D-parity, and full-three codes. This design methodology is applicable to any multiprocessor interconnection topology and the resulting FT designs have the same node degree as the non-FT target topology. We also analyze the deterministic fault tolerance for these designs and develop efficient layout strategies for them. Finally, we compare the proposed probabilistic designs to some of the best deterministic and probabilistic designs proposed in the past, and show that our designs can meet a given mean-time-to-failure (MTTF) specification at much lower hardware costs (switch complexity, redundant wiring area, and spare-processor overhead) than previous designs. Further, for a given number of spare processors, our designs have close-to-optimal reconfigurabilities that are much better than those of previous probabilistic designs.

Designing and embedding reliable virtual infrastructures

“…Furthermore, deriving optimal graphs G ′ with minimal links any general graph G has exponential complexity. To the best of the authors' knowledge, optimal solutions are found only on regular graphs such as lines, square-grids, circles, and trees [2,15,18].…”

“…At a fundamental level, there are methods to construct topologies for redundant nodes that address both nodes and links reliability [2,15]. Based on some input graph, additional links (or, bandwidth reservations) are introduced optimally such that the least number is needed.…”

Biologically inspired reconfigurable hardware for dependable applications

“…Most of hardware redundancy reconfiguration techniques rely on complex algorithms to re-assign physical resources to the elements of the logical array. In most cases these algorithms are executed by a central processor which also performs diagnosis functions and co-ordinates the reconfiguration of the physical array [6] [12] [8]. This approach has demonstrated to be effective, but its centralised nature makes it prone to collapse if the processor in charge of the fault tolerance functions fails.…”

Research accomplishments

“…1. I have developed a range of novel and efficient methodologies for designing fault-tolerant multiprocessors that include use of covering graphs and graph automorphisms, and a structural application of error correcting codes (ECCs) to yield multiprocessors with very high average fault tolerance [11,17,23,24,25,27,69,71,76,77,78,79]. In 1995, one of these papers [79] (published in 1988) was awarded the recognition of a most influential paper published in the first 25 years, 1971-1995, of the premier conference on fault-tolerant computing, the Fault Tolerant Computing Symp.…”