Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction , to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor , a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.
Aim of this paper is to propose a high-level power exploration framework based\ud
on an instruction-level energy model for VLIW (Very Long InstructionWord) architectures.\ud
More specifically, the present paper deals with the reduction of the complexity of the energy\ud
model of K-issueVLIWprocessors from exponential with respect to the number of operations\ud
within the Instruction Set O(|I SA|K ) to quadratic (O(K ∗ |I SA|2)). The complexity of the\ud
energy model has been further simplified by automatically clustering the operations in the ISA\ud
with respect to their average energy. Globally, the proposed approach reduces the complexity\ud
of the characterization problem for a K-issue VLIW processor to quadratic (O(K ∗ |C|2))\ud
with respect to the number of operation clusters. In this way, a more efficient characterization\ud
of the VLIW core power consumption can been achieved, while preserving the accuracy of\ud
the power estimates. The proposed model has been further extended to provide early power\ud
figures and energy/performance trade-offs for multi-cluster VLIW architectures composed of\ud
multiple data-path units and a single instruction cache control unit. The proposed high-level\ud
power estimation methodology has been applied to the Lx 4-issue VLIW pipelined processor\ud
provided by STMicroelectronics
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