System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip

Bona, Andrea; Zaccaria, Vittorio; Zafalon, R.

doi:10.1007/1-4020-8076-x_13

Cited by 16 publications

(17 citation statements)

References 10 publications

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“…Several approaches [9,21,22] have looked at analyzing power early in the design cycle, at the system level, for on-chip communication architectures. Some of these approaches have used the idea of creating energy macro-models from gate-level power/energy estimations, and applied it in the context of the AMBA AHB hierarchical shared bus architecture [9], STBus interconnection network [22] and NoCs [21].…”

Section: Related Workmentioning

confidence: 99%

“…Some of these approaches have used the idea of creating energy macro-models from gate-level power/energy estimations, and applied it in the context of the AMBA AHB hierarchical shared bus architecture [9], STBus interconnection network [22] and NoCs [21]. One of the goals of our work is to perform a detailed analysis of the bus matrix communication architecture to create such energy macro-models which can then be used in a system-level simulation environment for fast cycle energy/power estimation.…”

Section: Related Workmentioning

confidence: 99%

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System-level power-performance trade-offs in bus matrix communication architecture synthesis

Pasricha

Park

Kurdahi

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, powerperformance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macromodels into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macromodels incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

System-level power-performance trade-offs in bus matrix communication architecture synthesis

Pasricha

Park

Kurdahi

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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show abstract

“…Power models for on chip bus are described in [7]. [5] proposes a system level approach for power modelling of Network on chip. For component with regular implementations, such as memories, analytical models have been proposed to estimate power consumption under given access patterns [11].…”

Section: Related Workmentioning

confidence: 99%

Efficient High-Level Power Estimation for Multi-standard Wireless Systems

Ahmadinia

Ahmad

Arslan

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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This paper aims at providing a new system level power estimation methodology based on transaction level modelling (SystemC) for wireless applications, which can highly improve the trade-off between accuracy and efficiency of power estimation in system level. The main features of our novel simulation environment for SystemC will be presented, which allows the easy introduction of a power model in the executable specification of a sophisticated wireless design. It allows efficient power estimation of reconfigurable cores by state based power modelling, which leads to a viable solution for early power aware design of multistandard Wireless systems. The simulator has been applied to the SystemC modules of a WiMAX receiver based on ARM processor, reconfigurable FFT and Viterbi, and AMBA bus.

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“…For the cores we have used an instructionbased power model (see [31] for details). For the memories (both caches and private memories) we have used an analytical model derived from the work presented in [32], whereas the power model for the STbus interconnect has been taken from [33].…”

Section: The Multiprocessor Platformmentioning

confidence: 99%

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors

Loghi

Letis

Benini

et al. 2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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The performance of the various cache coherence protocols proposed in the literature have been extensively analyzed in the context of high-performance multi-processor systems. A similar analysis for Multi-Processor Systems-on-Chips (MPSoCs), where energy is at least as important as performace, and for which strict constraints on hardware and software resources do exist, has not been done yet. This work provides an effort in that sense, showing energy/performance tradeoffs for different snoop-based protocols on a realistic MPSoC architecture. The analysis leverage a multiprocessor simulation platform, augmented with accurate power models, that allows cycle-accurate simulations. Our analysis show that (i) cache write policy is actually more important than the actual cache coherence protocol, and (ii) matching the programming model and style to the architecture may have dramatic effects on the energy and performance of the system.

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System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip

Cited by 16 publications

References 10 publications

System-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix communication architecture synthesis

Efficient High-Level Power Estimation for Multi-standard Wireless Systems

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors

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