Objective: Indoor microclimate may affect students’ wellbeing, cardiac autonomic control and cognitive performance with potential impact on learning capabilities. To assess the effects of classroom temperature variations on the autonomic profile and students’ cognitive capabilities. Approach: Twenty students attending Humanitas University School, (14M, age 21  ±  3 years) underwent a single-lead ECG continuous recording by a portable device during a 2 h lecture when classroom temperature was set ‘neutral’ (20 °C–22 °C, Day 1) and when classroom temperature was set to 24 °C–26 °C (Day 2). ECGs were sent by telemetry to a server for off-line analysis. Spectral analysis of RR variability provided indices of cardiac sympathetic (LFnu), vagal (HF, HFnu) and cardiac sympatho-vagal modulation (LF/HF). Symbolic analysis of RR variability provided the percentage of sequences of three heart periods with no significant change in RR interval (0V%) and with two significant variations (2V%) reflecting cardiac sympathetic and vagal modulation, respectively. Students’ cognitive performance (memory, verbal comprehension and reasoning) was assessed at the end of each lecture using the Cambridge Brain Sciences cognitive evaluation tool. Main results: Classroom temperature and CO2 were assessed every 5 min. Classroom temperatures were 22.4 °C  ±  0.1 °C (Day 1) and 26.2 °C  ±  0.1 °C (Day 2). Student’s thermal comfort was lower during Day 2 compared to Day 1. HR, LF/HF and 0V% were greater during Day 2 (79.5  ±  12.1 bpm, 6.9  ±  7.1 and 32.8%  ±  10.3%) than during Day 1 (72.6  ±  10.8 bpm, 3.4  ±  3.7, 21.4%  ±  9.2%). Conversely, 2V% was lower during Day 2 (23.1%  ±  8.1%) than during Day 1 (32.3%  ±  11.4%). Short-term memory, verbal ability and the overall cognitive C-score scores were lower during Day 2 (10.3  ±  0.3; 8.1  ±  1.2 and 10.9  ±  2.0) compared to Day 1 (11.7  ±  2.1; 10.7  ±  1.7 and 12.6  ±  1.8). Significance: During Day 2, a shift of the cardiac autonomic control towards a sympathetic predominance was observed compared to Day 1, in the presence of greater thermal discomfort. Furthermore, during Day 2 reduced cognitive performances were found.

The advantages and the flexibility introduced into the hardware implementation by partial dynamic reconfiguration have rapidly changed the design flow of embedded systems. Although nowadays it is common to deal with systems characterized by a dynamic architecture able to manage and to adapt themselves to extremely different working scenarios, it is not so easy to provide such flexibility also into the software part of these systems. In order to cope with this problem we developed an innovative modular Linux driver that greatly simplifies the software handling of reconfiguration, allowing the programmer to concentrate on a hierarchical view of the system to be implemented. This methodology can be applied to different architectures providing a powerful and flexible software solution and, at the same time, it can be easily customized to respond to specific behaviors and requirement

No abstract

No abstract

No abstract

In high-performance systems, stencil computations play a crucial role as they appear in a variety of different fields of application, ranging from partial differential equation solving, to computer simulation of particles' interaction, to image processing and computer vision. The computationally intensive nature of those algorithms created the need for solutions to efficiently implement them in order to save both execution time and energy. This, in combination with their regular structure, has justified their widespread study and the proposal of largely different approaches to their optimization. However, most of these works are focused on aggressive compile time optimization, cache locality optimization, and parallelism extraction for the multicore/multiprocessor domain, while fewer works are focused on the exploitation of custom architectures to further exploit the regular structure of Iterative Stencil Loops (ISLs), specifically with the goal of improving power efficiency. This work introduces a methodology to systematically design power-efficient hardware accelerators for the optimal execution of ISL algorithms on Field-programmable Gate Arrays (FPGAs). As part of the methodology, we introduce the notion of Streaming Stencil Time-step (SST), a streaming-based architecture capable of achieving both low resource usage and efficient data reuse thanks to an optimal data buffering strategy, and we introduce a technique called SSTs queuing that is capable of delivering a pseudolinear execution time speedup with constant bandwidth. The methodology has been validated on significant benchmarks on a Virtex-7 FPGA using the Xilinx Vivado suite. Results demonstrate how the efficient usage of the on-chip memory resources realized by an SST allows one to treat problem sizes whose implementation would otherwise not be possible via direct synthesis of the original, unmanipulated code via High-Level Synthesis (HLS). We also show how the SSTs queuing effectively ensures a pseudolinear throughput speedup while consuming constant off-chip bandwidth. CCS Concepts: r Hardware → Hardware-software codesign; Methodologies for EDA; Sequential circuits; r Software and its engineering → Data flow architectures; r Theory of computation → Streaming models; Massively parallel algorithms;

Abstract-Designing applications for heterogeneous systems, like Multiprocessor System-on-Chips (MPSoCs) based on Field Programmable Gate Arrays (FPGAs) is a complex task. In order to exploit all the capabilities of these systems, such as Partial Dynamic Reconfiguration (PDR) and hardware acceleration, the designer still has to develop large parts of the system unassisted, establishing the design choices (i.e., whether to assign a task of the application on a hardware region of the FPGA or a general purpose processor of the SoC) mostly on his/her experience.In this paper we present a Mixed-Integer Linear Programming (MILP) formulation for mapping and scheduling of applications on heterogeneous and reconfigurable devices taking into account PDR, module reuse and configuration prefetching. Starting from a target architecture and a description of the application in terms of tasks and data dependencies, the proposed formulation allows the designer to optimize a linear combination of different metrics such as execution time, peak power and energy consumption.

No abstract