A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures

Deiana, Enrico Armenio; Rabozzi, Marco; Cattaneo, Riccardo; Santambrogio, Marco D.

doi:10.1109/reconfig.2015.7393328

Cited by 19 publications

(18 citation statements)

References 15 publications

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“…As a baseline situation, we solve the simplified scheduling problem, where the hardware resources are considered unlimited and every task module occupies an individual DRR, using an integer linear programming (ILP) formulation similar to that in [9]. The obtained T indicates the schedule length in the case when the configuration times are maximally hidden.…”

Section: B Results and Analysismentioning

confidence: 99%

“…All the aforementioned works mainly focus on partitioning/scheduling of the tasks without consideration of the floorplan, which will often cause the schedule to fail to be floorplanned effectively, as they do not consider the resource constraints on the FPGA chips. E. A. Deiana et al [9] proposed a mixed-integer linear programming (MILP) based scheduler for mapping and scheduling applications on partially reconfigurable FPGAs, and if the schedule cannot be successfully floorplanned, the scheduler is re-executed until a feasible floorplan is identified. However, the time-consuming MILP based method is impractical for large applications.…”

Section: A Related Workmentioning

confidence: 99%

“…In the ILP+Flooprlan method, we solve the ILP model once and run the floorplanning algorithm 10 times. Because the ILP based method is timeconsuming, we use the small test cases, t10, t30, and t50 (the largest test cases in [9] includes 50 tasks), for the comparison. N F represents that the ILP solver fails to find any feasible solution in a reasonable time.…”

Section: Vertically Aligning Drrs To Reconfigurable Framesmentioning

confidence: 99%

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Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Chen

Huang

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfiguration (PDR) technology is anticipated to accelerate the reconfiguration process and alleviate the device shortage. In this paper, we propose an integrated optimization framework for task partitioning, scheduling and floorplanning on partially dynamically reconfigurable FPGAs. The partition, schedule, and floorplan of the tasks are represented by the partitioned sequence triple P -ST (P S, QS, RS), where (P S, QS) is a hybrid nested sequence pair (HN SP ) for representing the spatial and temporal partitions, as well as the floorplan, and RS is the partitioned dynamic configuration order of the tasks. The floorplanning and scheduling of task modules can be computed from the partitioned sequence triple P -ST in O(n 2 ) time. To integrate the exploration of the scheduling and floorplanning design space, we use a simulated annealing-based search engine and elaborate a perturbation method, where a randomly chosen task module is removed from the partition sequence triple and then re-inserted into a proper position selected from all the O(n 3 ) possible combinations of partition, schedule and floorplan. We also prove a sufficient and necessary condition for the feasibility of the partitioning of tasks and scheduling of task configurations, and derive conditions for the feasibility of the insertion points in a P-ST. The experimental results demonstrate the efficiency and effectiveness of the proposed framework.

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Section: B Results and Analysismentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

Section: Vertically Aligning Drrs To Reconfigurable Framesmentioning

confidence: 99%

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Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Chen

Huang

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In the backend phase, CAOS produces both the runtime for executing the CPU functions and the final bitstreams needed to configure the FPGAs within the system, by leveraging the specific FPGA vendor tools (high-level synthesis and hardware synthesis tools) including Xilinx's SDAccel and Vivado HLS as well as MaxCompiler from Maxeler Technologies, based on the selected architectural template. Wherever possible, the backend can also support runtime reconfiguration of the FPGA devices through partial dynamic reconfiguration [90].…”

Section: ) Caosmentioning

confidence: 99%

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

et al. 2020

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Heterogeneous computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator that best matches its requirements and the system optimisation goals. This paper is motivated by the idea of a software tool that can automatically accomplish the task of deploying code, originally written for a conventional computer, to the processors and reconfigurable logic blocks in a heterogeneous system. We undertake an extensive survey of high-level synthesis tools to determine how close we are to this vision, and to identify any capability gaps. The survey is structured according to a new framework that clearly expresses the relationships between the many tools surveyed. We find that none of the existing tools can deploy general high-level code without manual intervention. Logic synthesis from arbitrary high-level code remains an open problem with dynamic data structures, function pointers and recursion all presenting challenges. Other challenges include automating the tasks of code partitioning, optimisation and design space exploration.

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“…In addition to studying the task placement on a single FPGA, some researchers have also studied the task scheduling in multi-FPGA systems. In [13], [14], the authors considered the mapping of tasks on a multi-FPGA system and the scheduling at execution time, which provided the references for our work. In [14], the authors further proposed a Mixed-Integer Linear Programming (MILP)-based algorithm.…”

Section: Related Workmentioning

confidence: 99%

Resource-Aware Task Scheduling and Placement in Multi-FPGA System

Sun

Zhang

2019

IEEE Access

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With the development of high performance computing, Field Programmable Gate Arrays (FPGAs) are widely used for task acceleration. Partial reconfigurable technology provides the possibility of multi-task concurrent computation on FPGAs. However, it is still difficult to achieve high performance multi-task acceleration in multi-FPGA systems due to the resource contention in limited hardware resources and reconfiguration overhead. In this paper, we propose a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. At the first scheduling stage, we select an appropriate computing unit for each task considering the subtask similarity and resource requirement similarity to reduce the possibility of reconfiguration and resource contention. At the second scheduling stage, we coordinate the subtask scheduling and placement to make full use of the hardware resources of FPGAs and improve the acceleration performance. Experiments show that our two-stage scheduling approach significantly reduces the tasks makespan and improves the utilization of resources compared with other traditional methods. INDEX TERMS Multi-FPGA, task scheduling, task placement, partial reconfiguration.

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A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures

Cited by 19 publications

References 15 publications

Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Resource-Aware Task Scheduling and Placement in Multi-FPGA System

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